xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,split.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display split
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display split, namely SPLIT, is used to split stream to two
15  encoders.
16  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8173-disp-split
26      - items:
27          - const: mediatek,mt6795-disp-split
28          - const: mediatek,mt8173-disp-split
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  power-domains:
37    description: A phandle and PM domain specifier as defined by bindings of
38      the power controller specified by phandle. See
39      Documentation/devicetree/bindings/power/power-domain.yaml for details.
40
41  clocks:
42    items:
43      - description: SPLIT Clock
44
45required:
46  - compatible
47  - reg
48  - power-domains
49  - clocks
50
51additionalProperties: false
52
53examples:
54  - |
55    #include <dt-bindings/clock/mt8173-clk.h>
56    #include <dt-bindings/power/mt8173-power.h>
57
58    soc {
59        #address-cells = <2>;
60        #size-cells = <2>;
61
62        split0: split@14018000 {
63            compatible = "mediatek,mt8173-disp-split";
64            reg = <0 0x14018000 0 0x1000>;
65            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
66            clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
67        };
68    };
69