xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,ovl.yaml (revision cb7aa33ac6cd46a5434798e50363136e64f3ae98) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overlay
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display overlay, namely OVL, can do alpha blending from
15  the memory.
16  OVL device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - const: mediatek,mt2701-disp-ovl
26      - items:
27          - const: mediatek,mt8173-disp-ovl
28      - items:
29          - const: mediatek,mt8183-disp-ovl
30      - items:
31          - const: mediatek,mt8192-disp-ovl
32      - items:
33          - enum:
34              - mediatek,mt7623-disp-ovl
35              - mediatek,mt2712-disp-ovl
36          - const: mediatek,mt2701-disp-ovl
37      - items:
38          - enum:
39              - mediatek,mt8188-disp-ovl
40              - mediatek,mt8195-disp-ovl
41          - const: mediatek,mt8183-disp-ovl
42      - items:
43          - enum:
44              - mediatek,mt8186-disp-ovl
45          - const: mediatek,mt8192-disp-ovl
46
47  reg:
48    maxItems: 1
49
50  interrupts:
51    maxItems: 1
52
53  power-domains:
54    description: A phandle and PM domain specifier as defined by bindings of
55      the power controller specified by phandle. See
56      Documentation/devicetree/bindings/power/power-domain.yaml for details.
57
58  clocks:
59    items:
60      - description: OVL Clock
61
62  iommus:
63    description:
64      This property should point to the respective IOMMU block with master port as argument,
65      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
66
67  mediatek,gce-client-reg:
68    description: The register of client driver can be configured by gce with
69      4 arguments defined in this property, such as phandle of gce, subsys id,
70      register offset and size. Each GCE subsys id is mapping to a client
71      defined in the header include/dt-bindings/gce/<chip>-gce.h.
72    $ref: /schemas/types.yaml#/definitions/phandle-array
73    maxItems: 1
74
75required:
76  - compatible
77  - reg
78  - interrupts
79  - power-domains
80  - clocks
81  - iommus
82
83additionalProperties: false
84
85examples:
86  - |
87    #include <dt-bindings/interrupt-controller/arm-gic.h>
88    #include <dt-bindings/clock/mt8173-clk.h>
89    #include <dt-bindings/power/mt8173-power.h>
90    #include <dt-bindings/gce/mt8173-gce.h>
91    #include <dt-bindings/memory/mt8173-larb-port.h>
92
93    soc {
94        #address-cells = <2>;
95        #size-cells = <2>;
96
97        ovl0: ovl@1400c000 {
98            compatible = "mediatek,mt8173-disp-ovl";
99            reg = <0 0x1400c000 0 0x1000>;
100            interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
101            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
102            clocks = <&mmsys CLK_MM_DISP_OVL0>;
103            iommus = <&iommu M4U_PORT_DISP_OVL0>;
104            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
105        };
106    };
107