xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,ovl.yaml (revision 02e9120893770924227138ba49df1edb3896112a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overlay
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display overlay, namely OVL, can do alpha blending from
15  the memory.
16  OVL device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt2701-disp-ovl
26          - mediatek,mt8173-disp-ovl
27          - mediatek,mt8183-disp-ovl
28          - mediatek,mt8192-disp-ovl
29      - items:
30          - enum:
31              - mediatek,mt7623-disp-ovl
32              - mediatek,mt2712-disp-ovl
33          - const: mediatek,mt2701-disp-ovl
34      - items:
35          - enum:
36              - mediatek,mt8188-disp-ovl
37              - mediatek,mt8195-disp-ovl
38          - const: mediatek,mt8183-disp-ovl
39      - items:
40          - enum:
41              - mediatek,mt8186-disp-ovl
42          - const: mediatek,mt8192-disp-ovl
43
44  reg:
45    maxItems: 1
46
47  interrupts:
48    maxItems: 1
49
50  power-domains:
51    description: A phandle and PM domain specifier as defined by bindings of
52      the power controller specified by phandle. See
53      Documentation/devicetree/bindings/power/power-domain.yaml for details.
54
55  clocks:
56    items:
57      - description: OVL Clock
58
59  iommus:
60    description:
61      This property should point to the respective IOMMU block with master port as argument,
62      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
63
64  mediatek,gce-client-reg:
65    description: The register of client driver can be configured by gce with
66      4 arguments defined in this property, such as phandle of gce, subsys id,
67      register offset and size. Each GCE subsys id is mapping to a client
68      defined in the header include/dt-bindings/gce/<chip>-gce.h.
69    $ref: /schemas/types.yaml#/definitions/phandle-array
70    maxItems: 1
71
72required:
73  - compatible
74  - reg
75  - interrupts
76  - power-domains
77  - clocks
78  - iommus
79
80additionalProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/interrupt-controller/arm-gic.h>
85    #include <dt-bindings/clock/mt8173-clk.h>
86    #include <dt-bindings/power/mt8173-power.h>
87    #include <dt-bindings/gce/mt8173-gce.h>
88    #include <dt-bindings/memory/mt8173-larb-port.h>
89
90    soc {
91        #address-cells = <2>;
92        #size-cells = <2>;
93
94        ovl0: ovl@1400c000 {
95            compatible = "mediatek,mt8173-disp-ovl";
96            reg = <0 0x1400c000 0 0x1000>;
97            interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
98            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
99            clocks = <&mmsys CLK_MM_DISP_OVL0>;
100            iommus = <&iommu M4U_PORT_DISP_OVL0>;
101            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
102        };
103    };
104