xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,mutex.yaml (revision 3a3af6b2a160bea72509a9d5ef84e25906b0478a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek mutex
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
15  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
16  data path or MDP data path.
17  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
18  the shadow register.
19  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
20  For a description of the MMSYS_CONFIG binding, see
21  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
22  for details.
23
24properties:
25  compatible:
26    oneOf:
27      - items:
28          - const: mediatek,mt2701-disp-mutex
29      - items:
30          - const: mediatek,mt2712-disp-mutex
31      - items:
32          - const: mediatek,mt8167-disp-mutex
33      - items:
34          - const: mediatek,mt8173-disp-mutex
35      - items:
36          - const: mediatek,mt8183-disp-mutex
37      - items:
38          - const: mediatek,mt8192-disp-mutex
39      - items:
40          - const: mediatek,mt8195-disp-mutex
41  reg:
42    maxItems: 1
43
44  interrupts:
45    maxItems: 1
46
47  power-domains:
48    description: A phandle and PM domain specifier as defined by bindings of
49      the power controller specified by phandle. See
50      Documentation/devicetree/bindings/power/power-domain.yaml for details.
51
52  clocks:
53    items:
54      - description: MUTEX Clock
55
56  mediatek,gce-events:
57    description:
58      The event id which is mapping to the specific hardware event signal
59      to gce. The event id is defined in the gce header
60      include/dt-bindings/gce/<chip>-gce.h of each chips.
61    $ref: /schemas/types.yaml#/definitions/uint32-array
62
63required:
64  - compatible
65  - reg
66  - interrupts
67  - power-domains
68  - clocks
69
70additionalProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/interrupt-controller/arm-gic.h>
75    #include <dt-bindings/clock/mt8173-clk.h>
76    #include <dt-bindings/power/mt8173-power.h>
77    #include <dt-bindings/gce/mt8173-gce.h>
78
79    soc {
80        #address-cells = <2>;
81        #size-cells = <2>;
82
83        mutex: mutex@14020000 {
84            compatible = "mediatek,mt8173-disp-mutex";
85            reg = <0 0x14020000 0 0x1000>;
86            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
87            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
88            clocks = <&mmsys CLK_MM_MUTEX_32K>;
89            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
90                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
91        };
92    };
93