xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,merge.yaml (revision fac71e4e09885bb2afa3d984a0c239a52e1a7418) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display merge
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15  inputs into one side-by-side output.
16  MERGE device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8173-disp-merge
26          - mediatek,mt8195-disp-merge
27
28  reg:
29    maxItems: 1
30
31  interrupts:
32    maxItems: 1
33
34  power-domains:
35    description: A phandle and PM domain specifier as defined by bindings of
36      the power controller specified by phandle. See
37      Documentation/devicetree/bindings/power/power-domain.yaml for details.
38
39  clocks:
40    minItems: 1
41    maxItems: 2
42
43  clock-names:
44    oneOf:
45      - items:
46          - const: merge
47      - items:
48          - const: merge
49          - const: merge_async
50
51  mediatek,merge-fifo-en:
52    description:
53      The setting of merge fifo is mainly provided for the display latency
54      buffer to ensure that the back-end panel display data will not be
55      underrun, a little more data is needed in the fifo.
56      According to the merge fifo settings, when the water level is detected
57      to be insufficient, it will trigger RDMA sending ultra and preulra
58      command to SMI to speed up the data rate.
59    type: boolean
60
61  mediatek,merge-mute:
62    description: Support mute function. Mute the content of merge output.
63    type: boolean
64
65  mediatek,gce-client-reg:
66    description: The register of client driver can be configured by gce with
67      4 arguments defined in this property, such as phandle of gce, subsys id,
68      register offset and size. Each GCE subsys id is mapping to a client
69      defined in the header include/dt-bindings/gce/<chip>-gce.h.
70    $ref: /schemas/types.yaml#/definitions/phandle-array
71    maxItems: 1
72
73  resets:
74    description: reset controller
75      See Documentation/devicetree/bindings/reset/reset.txt for details.
76    maxItems: 1
77
78required:
79  - compatible
80  - reg
81  - power-domains
82  - clocks
83
84additionalProperties: false
85
86examples:
87  - |
88    #include <dt-bindings/interrupt-controller/arm-gic.h>
89    #include <dt-bindings/clock/mt8173-clk.h>
90    #include <dt-bindings/power/mt8173-power.h>
91
92    soc {
93        #address-cells = <2>;
94        #size-cells = <2>;
95
96        merge@14017000 {
97            compatible = "mediatek,mt8173-disp-merge";
98            reg = <0 0x14017000 0 0x1000>;
99            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
100            clocks = <&mmsys CLK_MM_DISP_MERGE>;
101            clock-names = "merge";
102        };
103    };
104