xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,merge.yaml (revision af23369a6deaaeb612ab266eb88b8bb8d560c322) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display merge
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15  inputs into one side-by-side output.
16  MERGE device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - const: mediatek,mt8173-disp-merge
26      - items:
27          - const: mediatek,mt8195-disp-merge
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  power-domains:
36    description: A phandle and PM domain specifier as defined by bindings of
37      the power controller specified by phandle. See
38      Documentation/devicetree/bindings/power/power-domain.yaml for details.
39
40  clocks:
41    minItems: 1
42    maxItems: 2
43
44  clock-names:
45    oneOf:
46      - items:
47          - const: merge
48      - items:
49          - const: merge
50          - const: merge_async
51
52  mediatek,merge-fifo-en:
53    description:
54      The setting of merge fifo is mainly provided for the display latency
55      buffer to ensure that the back-end panel display data will not be
56      underrun, a little more data is needed in the fifo.
57      According to the merge fifo settings, when the water level is detected
58      to be insufficient, it will trigger RDMA sending ultra and preulra
59      command to SMI to speed up the data rate.
60    type: boolean
61
62  mediatek,merge-mute:
63    description: Support mute function. Mute the content of merge output.
64    type: boolean
65
66  mediatek,gce-client-reg:
67    description: The register of client driver can be configured by gce with
68      4 arguments defined in this property, such as phandle of gce, subsys id,
69      register offset and size. Each GCE subsys id is mapping to a client
70      defined in the header include/dt-bindings/gce/<chip>-gce.h.
71    $ref: /schemas/types.yaml#/definitions/phandle-array
72    maxItems: 1
73
74  resets:
75    description: reset controller
76      See Documentation/devicetree/bindings/reset/reset.txt for details.
77    maxItems: 1
78
79required:
80  - compatible
81  - reg
82  - power-domains
83  - clocks
84
85additionalProperties: false
86
87examples:
88  - |
89    #include <dt-bindings/interrupt-controller/arm-gic.h>
90    #include <dt-bindings/clock/mt8173-clk.h>
91    #include <dt-bindings/power/mt8173-power.h>
92
93    soc {
94        #address-cells = <2>;
95        #size-cells = <2>;
96
97        merge@14017000 {
98            compatible = "mediatek,mt8173-disp-merge";
99            reg = <0 0x14017000 0 0x1000>;
100            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
101            clocks = <&mmsys CLK_MM_DISP_MERGE>;
102            clock-names = "merge";
103        };
104    };
105