xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,merge.yaml (revision a0ca4af9455b844c5e094fc1b09b1390ffa979fc) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display merge
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15  inputs into one side-by-side output.
16  MERGE device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8173-disp-merge
26          - mediatek,mt8195-disp-merge
27          - mediatek,mt8195-mdp3-merge
28      - items:
29          - const: mediatek,mt6795-disp-merge
30          - const: mediatek,mt8173-disp-merge
31      - items:
32          - const: mediatek,mt8188-disp-merge
33          - const: mediatek,mt8195-disp-merge
34
35  reg:
36    maxItems: 1
37
38  interrupts:
39    maxItems: 1
40
41  power-domains:
42    description: A phandle and PM domain specifier as defined by bindings of
43      the power controller specified by phandle. See
44      Documentation/devicetree/bindings/power/power-domain.yaml for details.
45
46  clocks:
47    minItems: 1
48    maxItems: 2
49
50  clock-names:
51    oneOf:
52      - items:
53          - const: merge
54      - items:
55          - const: merge
56          - const: merge_async
57
58  mediatek,merge-fifo-en:
59    description:
60      The setting of merge fifo is mainly provided for the display latency
61      buffer to ensure that the back-end panel display data will not be
62      underrun, a little more data is needed in the fifo.
63      According to the merge fifo settings, when the water level is detected
64      to be insufficient, it will trigger RDMA sending ultra and preulra
65      command to SMI to speed up the data rate.
66    type: boolean
67
68  mediatek,merge-mute:
69    description: Support mute function. Mute the content of merge output.
70    type: boolean
71
72  mediatek,gce-client-reg:
73    description: The register of client driver can be configured by gce with
74      4 arguments defined in this property, such as phandle of gce, subsys id,
75      register offset and size. Each GCE subsys id is mapping to a client
76      defined in the header include/dt-bindings/gce/<chip>-gce.h.
77    $ref: /schemas/types.yaml#/definitions/phandle-array
78    maxItems: 1
79
80  resets:
81    description: reset controller
82      See Documentation/devicetree/bindings/reset/reset.txt for details.
83    maxItems: 1
84
85required:
86  - compatible
87  - reg
88  - power-domains
89  - clocks
90
91additionalProperties: false
92
93examples:
94  - |
95    #include <dt-bindings/interrupt-controller/arm-gic.h>
96    #include <dt-bindings/clock/mt8173-clk.h>
97    #include <dt-bindings/power/mt8173-power.h>
98
99    soc {
100        #address-cells = <2>;
101        #size-cells = <2>;
102
103        merge@14017000 {
104            compatible = "mediatek,mt8173-disp-merge";
105            reg = <0 0x14017000 0 0x1000>;
106            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
107            clocks = <&mmsys CLK_MM_DISP_MERGE>;
108            clock-names = "merge";
109        };
110    };
111