1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: mediatek DPI Controller Device Tree Bindings 8 9maintainers: 10 - CK Hu <ck.hu@mediatek.com> 11 - Jitao shi <jitao.shi@mediatek.com> 12 13description: | 14 The Mediatek DPI function block is a sink of the display subsystem and 15 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel 16 output bus. 17 18properties: 19 compatible: 20 enum: 21 - mediatek,mt2701-dpi 22 - mediatek,mt7623-dpi 23 - mediatek,mt8173-dpi 24 - mediatek,mt8183-dpi 25 - mediatek,mt8192-dpi 26 27 reg: 28 maxItems: 1 29 30 interrupts: 31 maxItems: 1 32 33 clocks: 34 items: 35 - description: Pixel Clock 36 - description: Engine Clock 37 - description: DPI PLL 38 39 clock-names: 40 items: 41 - const: pixel 42 - const: engine 43 - const: pll 44 45 pinctrl-0: true 46 pinctrl-1: true 47 48 pinctrl-names: 49 items: 50 - const: default 51 - const: sleep 52 53 port: 54 $ref: /schemas/graph.yaml#/properties/port 55 description: 56 Output port node. This port should be connected to the input port of an 57 attached HDMI or LVDS encoder chip. 58 59required: 60 - compatible 61 - reg 62 - interrupts 63 - clocks 64 - clock-names 65 - port 66 67additionalProperties: false 68 69examples: 70 - | 71 #include <dt-bindings/interrupt-controller/arm-gic.h> 72 #include <dt-bindings/clock/mt8173-clk.h> 73 74 dpi0: dpi@1401d000 { 75 compatible = "mediatek,mt8173-dpi"; 76 reg = <0x1401d000 0x1000>; 77 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 78 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 79 <&mmsys CLK_MM_DPI_ENGINE>, 80 <&apmixedsys CLK_APMIXED_TVDPLL>; 81 clock-names = "pixel", "engine", "pll"; 82 pinctrl-names = "default", "sleep"; 83 pinctrl-0 = <&dpi_pin_func>; 84 pinctrl-1 = <&dpi_pin_idle>; 85 86 port { 87 dpi0_out: endpoint { 88 remote-endpoint = <&hdmi0_in>; 89 }; 90 }; 91 }; 92 93... 94