xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dp.yaml (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Display Port Controller
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Jitao shi <jitao.shi@mediatek.com>
12
13description: |
14  MediaTek DP and eDP are different hardwares and there are some features
15  which are not supported for eDP. For example, audio is not supported for
16  eDP. Therefore, we need to use two different compatibles to describe them.
17  In addition, We just need to enable the power domain of DP, so the clock
18  of DP is generated by itself and we are not using other PLL to generate
19  clocks.
20
21properties:
22  compatible:
23    enum:
24      - mediatek,mt8188-dp-tx
25      - mediatek,mt8188-edp-tx
26      - mediatek,mt8195-dp-tx
27      - mediatek,mt8195-edp-tx
28
29  reg:
30    maxItems: 1
31
32  nvmem-cells:
33    maxItems: 1
34    description: efuse data for display port calibration
35
36  nvmem-cell-names:
37    const: dp_calibration_data
38
39  power-domains:
40    maxItems: 1
41
42  interrupts:
43    maxItems: 1
44
45  ports:
46    $ref: /schemas/graph.yaml#/properties/ports
47    properties:
48      port@0:
49        $ref: /schemas/graph.yaml#/properties/port
50        description: Input endpoint of the controller, usually dp_intf
51
52      port@1:
53        $ref: /schemas/graph.yaml#/$defs/port-base
54        unevaluatedProperties: false
55        description: Output endpoint of the controller
56        properties:
57          endpoint:
58            $ref: /schemas/media/video-interfaces.yaml#
59            unevaluatedProperties: false
60            properties:
61              data-lanes:
62                description: |
63                  number of lanes supported by the hardware.
64                  The possible values:
65                  0       - For 1 lane enabled in IP.
66                  0 1     - For 2 lanes enabled in IP.
67                  0 1 2 3 - For 4 lanes enabled in IP.
68                minItems: 1
69                maxItems: 4
70            required:
71              - data-lanes
72
73    required:
74      - port@0
75      - port@1
76
77  max-linkrate-mhz:
78    enum: [ 1620, 2700, 5400, 8100 ]
79    description: maximum link rate supported by the hardware.
80
81required:
82  - compatible
83  - reg
84  - interrupts
85  - ports
86  - max-linkrate-mhz
87
88additionalProperties: false
89
90examples:
91  - |
92    #include <dt-bindings/interrupt-controller/arm-gic.h>
93    #include <dt-bindings/power/mt8195-power.h>
94    dptx@1c600000 {
95        compatible = "mediatek,mt8195-dp-tx";
96        reg = <0x1c600000 0x8000>;
97        power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
98        interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
99        max-linkrate-mhz = <8100>;
100
101        ports {
102            #address-cells = <1>;
103            #size-cells = <0>;
104
105            port@0 {
106                reg = <0>;
107                dptx_in: endpoint {
108                    remote-endpoint = <&dp_intf0_out>;
109                };
110            };
111            port@1 {
112                reg = <1>;
113                dptx_out: endpoint {
114                    data-lanes = <0 1 2 3>;
115                };
116            };
117        };
118    };
119