1Mediatek display subsystem 2========================== 3 4The Mediatek display subsystem consists of various DISP function blocks in the 5MMSYS register space. The connections between them can be configured by output 6and input selectors in the MMSYS_CONFIG register space. Pixel clock and start 7of frame signal are distributed to the other function blocks by a DISP_MUTEX 8function block. 9 10All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node. 11For a description of the MMSYS_CONFIG binding, see 12Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml. 13 14DISP function blocks 15==================== 16 17A display stream starts at a source function block that reads pixel data from 18memory and ends with a sink function block that drives pixels on a display 19interface, or writes pixels back to memory. All DISP function blocks have 20their own register space, interrupt, and clock gate. The blocks that can 21access memory additionally have to list the IOMMU and local arbiter they are 22connected to. 23 24For a description of the display interface sink function blocks, see 25Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and 26Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml. 27 28Required properties (all function blocks): 29- compatible: "mediatek,<chip>-disp-<function>", one of 30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc) 31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc) 32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer 33 "mediatek,<chip>-disp-wdma" - write DMA 34 "mediatek,<chip>-disp-ccorr" - color correction 35 "mediatek,<chip>-disp-color" - color processor 36 "mediatek,<chip>-disp-dither" - dither 37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller 38 "mediatek,<chip>-disp-gamma" - gamma correction 39 "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources 40 "mediatek,<chip>-disp-postmask" - control round corner for display frame 41 "mediatek,<chip>-disp-split" - split stream to two encoders 42 "mediatek,<chip>-disp-ufoe" - data compression engine 43 "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt 44 "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt 45 "mediatek,<chip>-disp-mutex" - display mutex 46 "mediatek,<chip>-disp-od" - overdrive 47 the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192. 48- reg: Physical base address and length of the function block register space 49- interrupts: The interrupt signal from the function block (required, except for 50 merge and split function blocks). 51- clocks: device clocks 52 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 53 For most function blocks this is just a single clock input. Only the DSI and 54 DPI controller nodes have multiple clock inputs. These are documented in 55 mediatek,dsi.txt and mediatek,dpi.txt, respectively. 56 An exception is that the mt8183 mutex is always free running with no clocks property. 57 58Required properties (DMA function blocks): 59- compatible: Should be one of 60 "mediatek,<chip>-disp-ovl" 61 "mediatek,<chip>-disp-rdma" 62 "mediatek,<chip>-disp-wdma" 63 the supported chips are mt2701, mt8167 and mt8173. 64- larb: Should contain a phandle pointing to the local arbiter device as defined 65 in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml 66- iommus: Should point to the respective IOMMU block with master port as 67 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml 68 for details. 69 70Optional properties (RDMA function blocks): 71- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this 72 property to the corresponding rdma 73 the value is the Max value which defined in hardware data sheet. 74 mediatek,rdma-fifo-size of mt8173-rdma0 is 8K 75 mediatek,rdma-fifo-size of mt8183-rdma0 is 5K 76 mediatek,rdma-fifo-size of mt8183-rdma1 is 2K 77 78Examples: 79 80mmsys: clock-controller@14000000 { 81 compatible = "mediatek,mt8173-mmsys", "syscon"; 82 reg = <0 0x14000000 0 0x1000>; 83 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 84 #clock-cells = <1>; 85}; 86 87ovl0: ovl@1400c000 { 88 compatible = "mediatek,mt8173-disp-ovl"; 89 reg = <0 0x1400c000 0 0x1000>; 90 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 91 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 92 clocks = <&mmsys CLK_MM_DISP_OVL0>; 93 iommus = <&iommu M4U_PORT_DISP_OVL0>; 94 mediatek,larb = <&larb0>; 95}; 96 97ovl1: ovl@1400d000 { 98 compatible = "mediatek,mt8173-disp-ovl"; 99 reg = <0 0x1400d000 0 0x1000>; 100 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 101 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 102 clocks = <&mmsys CLK_MM_DISP_OVL1>; 103 iommus = <&iommu M4U_PORT_DISP_OVL1>; 104 mediatek,larb = <&larb4>; 105}; 106 107rdma0: rdma@1400e000 { 108 compatible = "mediatek,mt8173-disp-rdma"; 109 reg = <0 0x1400e000 0 0x1000>; 110 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 111 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 112 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 113 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 114 mediatek,larb = <&larb0>; 115 mediatek,rdma-fifosize = <8192>; 116}; 117 118rdma1: rdma@1400f000 { 119 compatible = "mediatek,mt8173-disp-rdma"; 120 reg = <0 0x1400f000 0 0x1000>; 121 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 122 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 123 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 124 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 125 mediatek,larb = <&larb4>; 126}; 127 128rdma2: rdma@14010000 { 129 compatible = "mediatek,mt8173-disp-rdma"; 130 reg = <0 0x14010000 0 0x1000>; 131 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 132 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 133 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 134 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 135 mediatek,larb = <&larb4>; 136}; 137 138wdma0: wdma@14011000 { 139 compatible = "mediatek,mt8173-disp-wdma"; 140 reg = <0 0x14011000 0 0x1000>; 141 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 142 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 143 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 144 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 145 mediatek,larb = <&larb0>; 146}; 147 148wdma1: wdma@14012000 { 149 compatible = "mediatek,mt8173-disp-wdma"; 150 reg = <0 0x14012000 0 0x1000>; 151 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 152 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 153 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 154 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 155 mediatek,larb = <&larb4>; 156}; 157 158color0: color@14013000 { 159 compatible = "mediatek,mt8173-disp-color"; 160 reg = <0 0x14013000 0 0x1000>; 161 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 162 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 163 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 164}; 165 166color1: color@14014000 { 167 compatible = "mediatek,mt8173-disp-color"; 168 reg = <0 0x14014000 0 0x1000>; 169 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 170 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 171 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 172}; 173 174aal@14015000 { 175 compatible = "mediatek,mt8173-disp-aal"; 176 reg = <0 0x14015000 0 0x1000>; 177 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 178 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 179 clocks = <&mmsys CLK_MM_DISP_AAL>; 180}; 181 182gamma@14016000 { 183 compatible = "mediatek,mt8173-disp-gamma"; 184 reg = <0 0x14016000 0 0x1000>; 185 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 186 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 187 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 188}; 189 190ufoe@1401a000 { 191 compatible = "mediatek,mt8173-disp-ufoe"; 192 reg = <0 0x1401a000 0 0x1000>; 193 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 194 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 195 clocks = <&mmsys CLK_MM_DISP_UFOE>; 196}; 197 198dsi0: dsi@1401b000 { 199 /* See mediatek,dsi.txt for details */ 200}; 201 202dpi0: dpi@1401d000 { 203 /* See mediatek,dpi.txt for details */ 204}; 205 206mutex: mutex@14020000 { 207 compatible = "mediatek,mt8173-disp-mutex"; 208 reg = <0 0x14020000 0 0x1000>; 209 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 210 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 211 clocks = <&mmsys CLK_MM_MUTEX_32K>; 212}; 213 214od@14023000 { 215 compatible = "mediatek,mt8173-disp-od"; 216 reg = <0 0x14023000 0 0x1000>; 217 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 218 clocks = <&mmsys CLK_MM_DISP_OD>; 219}; 220