xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsc.yaml (revision c9ccf3a32da427475985b85d7df023ccfb138c27)
1*c9ccf3a3SEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*c9ccf3a3SEmmanuel Vadot%YAML 1.2
3*c9ccf3a3SEmmanuel Vadot---
4*c9ccf3a3SEmmanuel Vadot$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
5*c9ccf3a3SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml#
6*c9ccf3a3SEmmanuel Vadot
7*c9ccf3a3SEmmanuel Vadottitle: mediatek display DSC controller
8*c9ccf3a3SEmmanuel Vadot
9*c9ccf3a3SEmmanuel Vadotmaintainers:
10*c9ccf3a3SEmmanuel Vadot  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11*c9ccf3a3SEmmanuel Vadot  - Philipp Zabel <p.zabel@pengutronix.de>
12*c9ccf3a3SEmmanuel Vadot
13*c9ccf3a3SEmmanuel Vadotdescription: |
14*c9ccf3a3SEmmanuel Vadot  The DSC standard is a specification of the algorithms used for
15*c9ccf3a3SEmmanuel Vadot  compressing and decompressing image display streams, including
16*c9ccf3a3SEmmanuel Vadot  the specification of the syntax and semantics of the compressed
17*c9ccf3a3SEmmanuel Vadot  video bit stream. DSC is designed for real-time systems with
18*c9ccf3a3SEmmanuel Vadot  real-time compression, transmission, decompression and Display.
19*c9ccf3a3SEmmanuel Vadot
20*c9ccf3a3SEmmanuel Vadotproperties:
21*c9ccf3a3SEmmanuel Vadot  compatible:
22*c9ccf3a3SEmmanuel Vadot    oneOf:
23*c9ccf3a3SEmmanuel Vadot      - items:
24*c9ccf3a3SEmmanuel Vadot          - const: mediatek,mt8195-disp-dsc
25*c9ccf3a3SEmmanuel Vadot
26*c9ccf3a3SEmmanuel Vadot  reg:
27*c9ccf3a3SEmmanuel Vadot    maxItems: 1
28*c9ccf3a3SEmmanuel Vadot
29*c9ccf3a3SEmmanuel Vadot  interrupts:
30*c9ccf3a3SEmmanuel Vadot    maxItems: 1
31*c9ccf3a3SEmmanuel Vadot
32*c9ccf3a3SEmmanuel Vadot  clocks:
33*c9ccf3a3SEmmanuel Vadot    items:
34*c9ccf3a3SEmmanuel Vadot      - description: DSC Wrapper Clock
35*c9ccf3a3SEmmanuel Vadot
36*c9ccf3a3SEmmanuel Vadot  power-domains:
37*c9ccf3a3SEmmanuel Vadot    description: A phandle and PM domain specifier as defined by bindings of
38*c9ccf3a3SEmmanuel Vadot      the power controller specified by phandle. See
39*c9ccf3a3SEmmanuel Vadot      Documentation/devicetree/bindings/power/power-domain.yaml for details.
40*c9ccf3a3SEmmanuel Vadot
41*c9ccf3a3SEmmanuel Vadot  mediatek,gce-client-reg:
42*c9ccf3a3SEmmanuel Vadot    description:
43*c9ccf3a3SEmmanuel Vadot      The register of client driver can be configured by gce with 4 arguments
44*c9ccf3a3SEmmanuel Vadot      defined in this property, such as phandle of gce, subsys id,
45*c9ccf3a3SEmmanuel Vadot      register offset and size.
46*c9ccf3a3SEmmanuel Vadot      Each subsys id is mapping to a base address of display function blocks
47*c9ccf3a3SEmmanuel Vadot      register which is defined in the gce header
48*c9ccf3a3SEmmanuel Vadot      include/dt-bindings/gce/<chip>-gce.h.
49*c9ccf3a3SEmmanuel Vadot    $ref: /schemas/types.yaml#/definitions/phandle-array
50*c9ccf3a3SEmmanuel Vadot    maxItems: 1
51*c9ccf3a3SEmmanuel Vadot
52*c9ccf3a3SEmmanuel Vadotrequired:
53*c9ccf3a3SEmmanuel Vadot  - compatible
54*c9ccf3a3SEmmanuel Vadot  - reg
55*c9ccf3a3SEmmanuel Vadot  - interrupts
56*c9ccf3a3SEmmanuel Vadot  - power-domains
57*c9ccf3a3SEmmanuel Vadot  - clocks
58*c9ccf3a3SEmmanuel Vadot
59*c9ccf3a3SEmmanuel VadotadditionalProperties: false
60*c9ccf3a3SEmmanuel Vadot
61*c9ccf3a3SEmmanuel Vadotexamples:
62*c9ccf3a3SEmmanuel Vadot  - |
63*c9ccf3a3SEmmanuel Vadot    #include <dt-bindings/interrupt-controller/arm-gic.h>
64*c9ccf3a3SEmmanuel Vadot    #include <dt-bindings/clock/mt8195-clk.h>
65*c9ccf3a3SEmmanuel Vadot    #include <dt-bindings/power/mt8195-power.h>
66*c9ccf3a3SEmmanuel Vadot    #include <dt-bindings/gce/mt8195-gce.h>
67*c9ccf3a3SEmmanuel Vadot
68*c9ccf3a3SEmmanuel Vadot    soc {
69*c9ccf3a3SEmmanuel Vadot        #address-cells = <2>;
70*c9ccf3a3SEmmanuel Vadot        #size-cells = <2>;
71*c9ccf3a3SEmmanuel Vadot
72*c9ccf3a3SEmmanuel Vadot        dsc0: disp_dsc_wrap@1c009000 {
73*c9ccf3a3SEmmanuel Vadot            compatible = "mediatek,mt8195-disp-dsc";
74*c9ccf3a3SEmmanuel Vadot            reg = <0 0x1c009000 0 0x1000>;
75*c9ccf3a3SEmmanuel Vadot            interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
76*c9ccf3a3SEmmanuel Vadot            power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
77*c9ccf3a3SEmmanuel Vadot            clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
78*c9ccf3a3SEmmanuel Vadot            mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
79*c9ccf3a3SEmmanuel Vadot        };
80*c9ccf3a3SEmmanuel Vadot    };
81