1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/lvds.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: LVDS Display Common Properties 8 9maintainers: 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11 - Thierry Reding <thierry.reding@gmail.com> 12 13description: |+ 14 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple 15 incompatible data link layers have been used over time to transmit image data 16 to LVDS devices. This bindings supports devices compatible with the following 17 specifications. 18 19 [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February 20 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) 21 [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National 22 Semiconductor 23 [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video 24 Electronics Standards Association (VESA) 25 26 Device compatible with those specifications have been marketed under the 27 FPD-Link and FlatLink brands. 28 29properties: 30 data-mapping: 31 enum: 32 - jeida-18 33 - jeida-24 34 - vesa-24 35 description: | 36 The color signals mapping order. 37 38 LVDS data mappings are defined as follows. 39 40 - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and 41 [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. 42 43 Slot 0 1 2 3 4 5 6 44 ________________ _________________ 45 Clock \_______________________/ 46 ______ ______ ______ ______ ______ ______ ______ 47 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 48 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 49 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 50 51 - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] 52 specifications. Data are transferred as follows on 4 LVDS lanes. 53 54 Slot 0 1 2 3 4 5 6 55 ________________ _________________ 56 Clock \_______________________/ 57 ______ ______ ______ ______ ______ ______ ______ 58 DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< 59 DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< 60 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< 61 DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 62 63 - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. 64 Data are transferred as follows on 4 LVDS lanes. 65 66 Slot 0 1 2 3 4 5 6 67 ________________ _________________ 68 Clock \_______________________/ 69 ______ ______ ______ ______ ______ ______ ______ 70 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 71 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 72 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 73 DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 74 75 Control signals are mapped as follows. 76 77 CTL0: HSync 78 CTL1: VSync 79 CTL2: Data Enable 80 CTL3: 0 81 82 data-mirror: 83 type: boolean 84 description: 85 If set, reverse the bit order described in the data mappings below on all 86 data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6. 87 88additionalProperties: true 89 90... 91