1*84943d6fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*84943d6fSEmmanuel Vadot%YAML 1.2 3*84943d6fSEmmanuel Vadot--- 4*84943d6fSEmmanuel Vadot$id: http://devicetree.org/schemas/display/lvds-data-mapping.yaml# 5*84943d6fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*84943d6fSEmmanuel Vadot 7*84943d6fSEmmanuel Vadottitle: LVDS Data Mapping 8*84943d6fSEmmanuel Vadot 9*84943d6fSEmmanuel Vadotmaintainers: 10*84943d6fSEmmanuel Vadot - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11*84943d6fSEmmanuel Vadot - Thierry Reding <thierry.reding@gmail.com> 12*84943d6fSEmmanuel Vadot 13*84943d6fSEmmanuel Vadotdescription: | 14*84943d6fSEmmanuel Vadot LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple 15*84943d6fSEmmanuel Vadot incompatible data link layers have been used over time to transmit image data 16*84943d6fSEmmanuel Vadot to LVDS devices. This bindings supports devices compatible with the following 17*84943d6fSEmmanuel Vadot specifications. 18*84943d6fSEmmanuel Vadot 19*84943d6fSEmmanuel Vadot [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February 20*84943d6fSEmmanuel Vadot 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) 21*84943d6fSEmmanuel Vadot [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National 22*84943d6fSEmmanuel Vadot Semiconductor 23*84943d6fSEmmanuel Vadot [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video 24*84943d6fSEmmanuel Vadot Electronics Standards Association (VESA) 25*84943d6fSEmmanuel Vadot 26*84943d6fSEmmanuel Vadot Device compatible with those specifications have been marketed under the 27*84943d6fSEmmanuel Vadot FPD-Link and FlatLink brands. 28*84943d6fSEmmanuel Vadot 29*84943d6fSEmmanuel Vadotproperties: 30*84943d6fSEmmanuel Vadot data-mapping: 31*84943d6fSEmmanuel Vadot enum: 32*84943d6fSEmmanuel Vadot - jeida-18 33*84943d6fSEmmanuel Vadot - jeida-24 34*84943d6fSEmmanuel Vadot - vesa-24 35*84943d6fSEmmanuel Vadot description: | 36*84943d6fSEmmanuel Vadot The color signals mapping order. 37*84943d6fSEmmanuel Vadot 38*84943d6fSEmmanuel Vadot LVDS data mappings are defined as follows. 39*84943d6fSEmmanuel Vadot 40*84943d6fSEmmanuel Vadot - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and 41*84943d6fSEmmanuel Vadot [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. 42*84943d6fSEmmanuel Vadot 43*84943d6fSEmmanuel Vadot Slot 0 1 2 3 4 5 6 44*84943d6fSEmmanuel Vadot ________________ _________________ 45*84943d6fSEmmanuel Vadot Clock \_______________________/ 46*84943d6fSEmmanuel Vadot ______ ______ ______ ______ ______ ______ ______ 47*84943d6fSEmmanuel Vadot DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 48*84943d6fSEmmanuel Vadot DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 49*84943d6fSEmmanuel Vadot DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 50*84943d6fSEmmanuel Vadot 51*84943d6fSEmmanuel Vadot - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] 52*84943d6fSEmmanuel Vadot specifications. Data are transferred as follows on 4 LVDS lanes. 53*84943d6fSEmmanuel Vadot 54*84943d6fSEmmanuel Vadot Slot 0 1 2 3 4 5 6 55*84943d6fSEmmanuel Vadot ________________ _________________ 56*84943d6fSEmmanuel Vadot Clock \_______________________/ 57*84943d6fSEmmanuel Vadot ______ ______ ______ ______ ______ ______ ______ 58*84943d6fSEmmanuel Vadot DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< 59*84943d6fSEmmanuel Vadot DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< 60*84943d6fSEmmanuel Vadot DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< 61*84943d6fSEmmanuel Vadot DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 62*84943d6fSEmmanuel Vadot 63*84943d6fSEmmanuel Vadot - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. 64*84943d6fSEmmanuel Vadot Data are transferred as follows on 4 LVDS lanes. 65*84943d6fSEmmanuel Vadot 66*84943d6fSEmmanuel Vadot Slot 0 1 2 3 4 5 6 67*84943d6fSEmmanuel Vadot ________________ _________________ 68*84943d6fSEmmanuel Vadot Clock \_______________________/ 69*84943d6fSEmmanuel Vadot ______ ______ ______ ______ ______ ______ ______ 70*84943d6fSEmmanuel Vadot DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 71*84943d6fSEmmanuel Vadot DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 72*84943d6fSEmmanuel Vadot DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 73*84943d6fSEmmanuel Vadot DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 74*84943d6fSEmmanuel Vadot 75*84943d6fSEmmanuel Vadot Control signals are mapped as follows. 76*84943d6fSEmmanuel Vadot 77*84943d6fSEmmanuel Vadot CTL0: HSync 78*84943d6fSEmmanuel Vadot CTL1: VSync 79*84943d6fSEmmanuel Vadot CTL2: Data Enable 80*84943d6fSEmmanuel Vadot CTL3: 0 81*84943d6fSEmmanuel Vadot 82*84943d6fSEmmanuel VadotadditionalProperties: true 83*84943d6fSEmmanuel Vadot 84*84943d6fSEmmanuel Vadot... 85