xref: /freebsd/sys/contrib/device-tree/Bindings/display/imx/nxp,imx8mq-dcss.yaml (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 NXP
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: iMX8MQ Display Controller Subsystem (DCSS)
9
10maintainers:
11  - Laurentiu Palcu <laurentiu.palcu@nxp.com>
12
13description:
14
15  The DCSS (display controller sub system) is used to source up to three
16  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
17  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
18  image processing capabilities are included to provide a solution capable of
19  driving next generation high dynamic range displays.
20
21properties:
22  compatible:
23    const: nxp,imx8mq-dcss
24
25  reg:
26    items:
27      - description: DCSS base address and size, up to IRQ steer start
28      - description: DCSS BLKCTL base address and size
29
30  interrupts:
31    items:
32      - description: Context loader completion and error interrupt
33      - description: DTG interrupt used to signal context loader trigger time
34      - description: DTG interrupt for Vblank
35
36  interrupt-names:
37    items:
38      - const: ctxld
39      - const: ctxld_kick
40      - const: vblank
41
42  clocks:
43    items:
44      - description: Display APB clock for all peripheral PIO access interfaces
45      - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
46      - description: RTRAM clock
47      - description: Pixel clock, can be driven either by HDMI phy clock or MIPI
48      - description: DTRC clock, needed by video decompressor
49
50  clock-names:
51    items:
52      - const: apb
53      - const: axi
54      - const: rtrm
55      - const: pix
56      - const: dtrc
57
58  assigned-clocks:
59    items:
60      - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
61      - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
62      - description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
63                     IMX8MQ_VIDEO_PLL1_REF_SEL
64
65  assigned-clock-parents:
66    items:
67      - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
68      - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
69      - description: Phandle and clock specifier of IMX8MQ_CLK_27M
70
71  assigned-clock-rates:
72    items:
73      - description: Must be 800 MHz
74      - description: Must be 400 MHz
75
76  port:
77    $ref: /schemas/graph.yaml#/properties/port
78    description:
79      A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
80
81additionalProperties: false
82
83examples:
84  - |
85    #include <dt-bindings/clock/imx8mq-clock.h>
86    dcss: display-controller@32e00000 {
87        compatible = "nxp,imx8mq-dcss";
88        reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
89        interrupts = <6>, <8>, <9>;
90        interrupt-names = "ctxld", "ctxld_kick", "vblank";
91        interrupt-parent = <&irqsteer>;
92        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
93                 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
94                 <&clk IMX8MQ_CLK_DISP_DTRC>;
95        clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
96        assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
97                          <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
98        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
99                                 <&clk IMX8MQ_CLK_27M>;
100        assigned-clock-rates = <800000000>,
101                               <400000000>;
102        port {
103            dcss_out: endpoint {
104                remote-endpoint = <&hdmi_in>;
105            };
106        };
107    };
108