1*833e5d42SEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*833e5d42SEmmanuel Vadot%YAML 1.2 3*833e5d42SEmmanuel Vadot--- 4*833e5d42SEmmanuel Vadot$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml# 5*833e5d42SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*833e5d42SEmmanuel Vadot 7*833e5d42SEmmanuel Vadottitle: Freescale i.MX8qxp Display Controller Command Sequencer 8*833e5d42SEmmanuel Vadot 9*833e5d42SEmmanuel Vadotdescription: | 10*833e5d42SEmmanuel Vadot The Command Sequencer is designed to autonomously process command lists. 11*833e5d42SEmmanuel Vadot By that it can load setups into the DC configuration and synchronize to 12*833e5d42SEmmanuel Vadot hardware events. This releases a system's CPU from workload, because it 13*833e5d42SEmmanuel Vadot does not need to wait for certain events. Also it simplifies SW architecture, 14*833e5d42SEmmanuel Vadot because no interrupt handlers are required. Setups are read via AXI bus, 15*833e5d42SEmmanuel Vadot while write access to configuration registers occurs directly via an internal 16*833e5d42SEmmanuel Vadot bus. This saves bandwidth for the AXI interconnect and improves the system 17*833e5d42SEmmanuel Vadot architecture in terms of safety aspects. 18*833e5d42SEmmanuel Vadot 19*833e5d42SEmmanuel Vadotmaintainers: 20*833e5d42SEmmanuel Vadot - Liu Ying <victor.liu@nxp.com> 21*833e5d42SEmmanuel Vadot 22*833e5d42SEmmanuel Vadotproperties: 23*833e5d42SEmmanuel Vadot compatible: 24*833e5d42SEmmanuel Vadot const: fsl,imx8qxp-dc-command-sequencer 25*833e5d42SEmmanuel Vadot 26*833e5d42SEmmanuel Vadot reg: 27*833e5d42SEmmanuel Vadot maxItems: 1 28*833e5d42SEmmanuel Vadot 29*833e5d42SEmmanuel Vadot clocks: 30*833e5d42SEmmanuel Vadot maxItems: 1 31*833e5d42SEmmanuel Vadot 32*833e5d42SEmmanuel Vadot interrupts: 33*833e5d42SEmmanuel Vadot maxItems: 5 34*833e5d42SEmmanuel Vadot 35*833e5d42SEmmanuel Vadot interrupt-names: 36*833e5d42SEmmanuel Vadot items: 37*833e5d42SEmmanuel Vadot - const: error 38*833e5d42SEmmanuel Vadot - const: sw0 39*833e5d42SEmmanuel Vadot - const: sw1 40*833e5d42SEmmanuel Vadot - const: sw2 41*833e5d42SEmmanuel Vadot - const: sw3 42*833e5d42SEmmanuel Vadot 43*833e5d42SEmmanuel Vadot sram: 44*833e5d42SEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/phandle 45*833e5d42SEmmanuel Vadot description: phandle pointing to the mmio-sram device node 46*833e5d42SEmmanuel Vadot 47*833e5d42SEmmanuel Vadotrequired: 48*833e5d42SEmmanuel Vadot - compatible 49*833e5d42SEmmanuel Vadot - reg 50*833e5d42SEmmanuel Vadot - clocks 51*833e5d42SEmmanuel Vadot - interrupts 52*833e5d42SEmmanuel Vadot - interrupt-names 53*833e5d42SEmmanuel Vadot 54*833e5d42SEmmanuel VadotadditionalProperties: false 55*833e5d42SEmmanuel Vadot 56*833e5d42SEmmanuel Vadotexamples: 57*833e5d42SEmmanuel Vadot - | 58*833e5d42SEmmanuel Vadot #include <dt-bindings/clock/imx8-lpcg.h> 59*833e5d42SEmmanuel Vadot 60*833e5d42SEmmanuel Vadot command-sequencer@56180400 { 61*833e5d42SEmmanuel Vadot compatible = "fsl,imx8qxp-dc-command-sequencer"; 62*833e5d42SEmmanuel Vadot reg = <0x56180400 0x1a4>; 63*833e5d42SEmmanuel Vadot clocks = <&dc0_lpcg IMX_LPCG_CLK_5>; 64*833e5d42SEmmanuel Vadot interrupt-parent = <&dc0_intc>; 65*833e5d42SEmmanuel Vadot interrupts = <36>, <37>, <38>, <39>, <40>; 66*833e5d42SEmmanuel Vadot interrupt-names = "error", "sw0", "sw1", "sw2", "sw3"; 67*833e5d42SEmmanuel Vadot }; 68