1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface 8 9maintainers: 10 - Liu Ying <victor.liu@nxp.com> 11 12description: | 13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI) 14 interfaces the pixel link 36-bit data output and the DSI controller’s 15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module 16 used in LVDS mode, to remap the pixel color codings between those modules. 17 This module is purely combinatorial. 18 19 The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module. 20 The CSR module, as a system controller, contains the PXL2DPI's configuration 21 register. 22 23properties: 24 compatible: 25 const: fsl,imx8qxp-pxl2dpi 26 27 fsl,sc-resource: 28 $ref: /schemas/types.yaml#/definitions/uint32 29 description: The SCU resource ID associated with this PXL2DPI instance. 30 31 power-domains: 32 maxItems: 1 33 34 fsl,companion-pxl2dpi: 35 $ref: /schemas/types.yaml#/definitions/phandle 36 description: | 37 A phandle which points to companion PXL2DPI which is used by downstream 38 LVDS Display Bridge(LDB) in split mode. 39 40 ports: 41 $ref: /schemas/graph.yaml#/properties/ports 42 43 properties: 44 port@0: 45 $ref: /schemas/graph.yaml#/properties/port 46 description: The PXL2DPI input port node from pixel link. 47 48 port@1: 49 $ref: /schemas/graph.yaml#/properties/port 50 description: The PXL2DPI output port node to downstream bridge. 51 52 required: 53 - port@0 54 - port@1 55 56required: 57 - compatible 58 - fsl,sc-resource 59 - power-domains 60 - ports 61 62additionalProperties: false 63 64examples: 65 - | 66 #include <dt-bindings/firmware/imx/rsrc.h> 67 pxl2dpi { 68 compatible = "fsl,imx8qxp-pxl2dpi"; 69 fsl,sc-resource = <IMX_SC_R_MIPI_0>; 70 power-domains = <&pd IMX_SC_R_MIPI_0>; 71 72 ports { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 port@0 { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 reg = <0>; 80 81 mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 { 82 reg = <0>; 83 remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>; 84 }; 85 86 mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 { 87 reg = <1>; 88 remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>; 89 }; 90 }; 91 92 port@1 { 93 #address-cells = <1>; 94 #size-cells = <0>; 95 reg = <1>; 96 97 mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { 98 reg = <0>; 99 remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; 100 }; 101 102 mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { 103 reg = <1>; 104 remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; 105 }; 106 }; 107 }; 108 }; 109