xref: /freebsd/sys/contrib/device-tree/Bindings/display/bridge/fsl,imx8qxp-ldb.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX8qm/qxp LVDS Display Bridge
8
9maintainers:
10  - Liu Ying <victor.liu@nxp.com>
11
12description: |
13  The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
14
15  The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
16  The CSR module, as a system controller, contains the LDB's configuration
17  registers.
18
19  For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
20  format and can map the input to VESA or JEIDA standards.  The two channels
21  cannot be used simultaneously, that is to say, the user should pick one of
22  them to use.  Two LDB channels from two LDB instances can work together in
23  LDB split mode to support a dual link LVDS display.  The channel indexes
24  have to be different.  Channel0 outputs odd pixels and channel1 outputs
25  even pixels.
26
27  For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
28  input color format.  The two channels can be used simultaneously, either
29  in dual mode or split mode.  In dual mode, the two channels output identical
30  data.  In split mode, channel0 outputs odd pixels and channel1 outputs even
31  pixels.
32
33  A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
34  the SoC reference manuals.  The pixel mapper uses logic of LDBs embedded in
35  i.MX6qdl/sx SoCs, i.e., it is essentially based on them.  To keep the naming
36  consistency, this binding calls it LDB.
37
38properties:
39  compatible:
40    enum:
41      - fsl,imx8qm-ldb
42      - fsl,imx8qxp-ldb
43
44  "#address-cells":
45    const: 1
46
47  "#size-cells":
48    const: 0
49
50  clocks:
51    items:
52      - description: pixel clock
53      - description: bypass clock
54
55  clock-names:
56    items:
57      - const: pixel
58      - const: bypass
59
60  power-domains:
61    maxItems: 1
62
63  fsl,companion-ldb:
64    $ref: /schemas/types.yaml#/definitions/phandle
65    description: |
66      A phandle which points to companion LDB which is used in LDB split mode.
67
68patternProperties:
69  "^channel@[0-1]$":
70    type: object
71    description: Represents a channel of LDB.
72
73    properties:
74      "#address-cells":
75        const: 1
76
77      "#size-cells":
78        const: 0
79
80      reg:
81        description: The channel index.
82        enum: [ 0, 1 ]
83
84      phys:
85        description: A phandle to the phy module representing the LVDS PHY.
86        maxItems: 1
87
88      phy-names:
89        const: lvds_phy
90
91      port@0:
92        $ref: /schemas/graph.yaml#/properties/port
93        description: Input port of the channel.
94
95      port@1:
96        $ref: /schemas/graph.yaml#/properties/port
97        description: Output port of the channel.
98
99    required:
100      - "#address-cells"
101      - "#size-cells"
102      - reg
103      - phys
104      - phy-names
105
106    additionalProperties: false
107
108required:
109  - compatible
110  - "#address-cells"
111  - "#size-cells"
112  - clocks
113  - clock-names
114  - power-domains
115  - channel@0
116  - channel@1
117
118allOf:
119  - if:
120      properties:
121        compatible:
122          contains:
123            const: fsl,imx8qm-ldb
124    then:
125      properties:
126        fsl,companion-ldb: false
127
128additionalProperties: false
129
130examples:
131  - |
132    #include <dt-bindings/firmware/imx/rsrc.h>
133    ldb {
134        #address-cells = <1>;
135        #size-cells = <0>;
136        compatible = "fsl,imx8qxp-ldb";
137        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
138                 <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
139        clock-names = "pixel", "bypass";
140        power-domains = <&pd IMX_SC_R_LVDS_0>;
141
142        channel@0 {
143            #address-cells = <1>;
144            #size-cells = <0>;
145            reg = <0>;
146            phys = <&mipi_lvds_0_phy>;
147            phy-names = "lvds_phy";
148
149            port@0 {
150                reg = <0>;
151
152                mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
153                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
154                };
155            };
156        };
157
158        channel@1 {
159            #address-cells = <1>;
160            #size-cells = <0>;
161            reg = <1>;
162            phys = <&mipi_lvds_0_phy>;
163            phy-names = "lvds_phy";
164
165            port@0 {
166                reg = <0>;
167
168                mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
169                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
170                };
171            };
172        };
173    };
174