1Cadence DSI bridge 2================== 3 4The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes. 5 6Required properties: 7- compatible: should be set to "cdns,dsi". 8- reg: physical base address and length of the controller's registers. 9- interrupts: interrupt line connected to the DSI bridge. 10- clocks: DSI bridge clocks. 11- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk". 12- phys: phandle link to the MIPI D-PHY controller. 13- phy-names: must contain "dphy". 14- #address-cells: must be set to 1. 15- #size-cells: must be set to 0. 16 17Optional properties: 18- resets: DSI reset lines. 19- reset-names: can contain "dsi_p_rst". 20 21Required subnodes: 22- ports: Ports as described in Documentation/devicetree/bindings/graph.txt. 23 2 ports are available: 24 * port 0: this port is only needed if some of your DSI devices are 25 controlled through an external bus like I2C or SPI. Can have at 26 most 4 endpoints. The endpoint number is directly encoding the 27 DSI virtual channel used by this device. 28 * port 1: represents the DPI input. 29 Other ports will be added later to support the new kind of inputs. 30 31- one subnode per DSI device connected on the DSI bus. Each DSI device should 32 contain a reg property encoding its virtual channel. 33 34Example: 35 dsi0: dsi@fd0c0000 { 36 compatible = "cdns,dsi"; 37 reg = <0x0 0xfd0c0000 0x0 0x1000>; 38 clocks = <&pclk>, <&sysclk>; 39 clock-names = "dsi_p_clk", "dsi_sys_clk"; 40 interrupts = <1>; 41 phys = <&dphy0>; 42 phy-names = "dphy"; 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 ports { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 port@1 { 51 reg = <1>; 52 dsi0_dpi_input: endpoint { 53 remote-endpoint = <&xxx_dpi_output>; 54 }; 55 }; 56 }; 57 58 panel: dsi-dev@0 { 59 compatible = "<vendor,panel>"; 60 reg = <0>; 61 }; 62 }; 63 64or 65 66 dsi0: dsi@fd0c0000 { 67 compatible = "cdns,dsi"; 68 reg = <0x0 0xfd0c0000 0x0 0x1000>; 69 clocks = <&pclk>, <&sysclk>; 70 clock-names = "dsi_p_clk", "dsi_sys_clk"; 71 interrupts = <1>; 72 phys = <&dphy1>; 73 phy-names = "dphy"; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 ports { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 port@0 { 82 reg = <0>; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 dsi0_output: endpoint@0 { 87 reg = <0>; 88 remote-endpoint = <&dsi_panel_input>; 89 }; 90 }; 91 92 port@1 { 93 reg = <1>; 94 dsi0_dpi_input: endpoint { 95 remote-endpoint = <&xxx_dpi_output>; 96 }; 97 }; 98 }; 99 }; 100 101 i2c@xxx { 102 panel: panel@59 { 103 compatible = "<vendor,panel>"; 104 reg = <0x59>; 105 106 port { 107 dsi_panel_input: endpoint { 108 remote-endpoint = <&dsi0_output>; 109 }; 110 }; 111 }; 112 }; 113