1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/brcm,bcm2835-dsi0.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Broadcom VC4 (VideoCore4) DSI Controller 8 9maintainers: 10 - Eric Anholt <eric@anholt.net> 11 12allOf: 13 - $ref: dsi-controller.yaml# 14 15properties: 16 "#clock-cells": 17 const: 1 18 19 compatible: 20 enum: 21 - brcm,bcm2711-dsi1 22 - brcm,bcm2835-dsi0 23 - brcm,bcm2835-dsi1 24 25 reg: 26 maxItems: 1 27 28 clocks: 29 items: 30 - description: The DSI PLL clock feeding the DSI analog PHY 31 - description: The DSI ESC clock 32 - description: The DSI pixel clock 33 34 clock-names: 35 items: 36 - const: phy 37 - const: escape 38 - const: pixel 39 40 clock-output-names: true 41 # FIXME: The meta-schemas don't seem to allow it for now 42 # items: 43 # - description: The DSI byte clock for the PHY 44 # - description: The DSI DDR2 clock 45 # - description: The DSI DDR clock 46 47 interrupts: 48 maxItems: 1 49 50 power-domains: 51 maxItems: 1 52 53required: 54 - "#clock-cells" 55 - compatible 56 - reg 57 - clocks 58 - clock-names 59 - clock-output-names 60 - interrupts 61 62unevaluatedProperties: false 63 64examples: 65 - | 66 #include <dt-bindings/clock/bcm2835.h> 67 68 dsi1: dsi@7e700000 { 69 compatible = "brcm,bcm2835-dsi1"; 70 reg = <0x7e700000 0x8c>; 71 interrupts = <2 12>; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 #clock-cells = <1>; 75 76 clocks = <&clocks BCM2835_PLLD_DSI1>, 77 <&clocks BCM2835_CLOCK_DSI1E>, 78 <&clocks BCM2835_CLOCK_DSI1P>; 79 clock-names = "phy", "escape", "pixel"; 80 81 clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr"; 82 83 }; 84 85... 86