1*c66ec88fSEmmanuel VadotARM HDLCD 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThis is a display controller found on several development platforms produced 4*c66ec88fSEmmanuel Vadotby ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB 5*c66ec88fSEmmanuel Vadotstreamer that reads the data from a framebuffer and sends it to a single 6*c66ec88fSEmmanuel Vadotdigital encoder (DVI or HDMI). 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel VadotRequired properties: 9*c66ec88fSEmmanuel Vadot - compatible: "arm,hdlcd" 10*c66ec88fSEmmanuel Vadot - reg: Physical base address and length of the controller's registers. 11*c66ec88fSEmmanuel Vadot - interrupts: One interrupt used by the display controller to notify the 12*c66ec88fSEmmanuel Vadot interrupt controller when any of the interrupt sources programmed in 13*c66ec88fSEmmanuel Vadot the interrupt mask register have activated. 14*c66ec88fSEmmanuel Vadot - clocks: A list of phandle + clock-specifier pairs, one for each 15*c66ec88fSEmmanuel Vadot entry in 'clock-names'. 16*c66ec88fSEmmanuel Vadot - clock-names: A list of clock names. For HDLCD it should contain: 17*c66ec88fSEmmanuel Vadot - "pxlclk" for the clock feeding the output PLL of the controller. 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel VadotRequired sub-nodes: 20*c66ec88fSEmmanuel Vadot - port: The HDLCD connection to an encoder chip. The connection is modeled 21*c66ec88fSEmmanuel Vadot using the OF graph bindings specified in 22*c66ec88fSEmmanuel Vadot Documentation/devicetree/bindings/graph.txt. 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel VadotOptional properties: 25*c66ec88fSEmmanuel Vadot - memory-region: phandle to a node describing memory (see 26*c66ec88fSEmmanuel Vadot Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be 27*c66ec88fSEmmanuel Vadot used for the framebuffer; if not present, the framebuffer may be located 28*c66ec88fSEmmanuel Vadot anywhere in memory. 29*c66ec88fSEmmanuel Vadot 30*c66ec88fSEmmanuel Vadot 31*c66ec88fSEmmanuel VadotExample: 32*c66ec88fSEmmanuel Vadot 33*c66ec88fSEmmanuel Vadot/ { 34*c66ec88fSEmmanuel Vadot ... 35*c66ec88fSEmmanuel Vadot 36*c66ec88fSEmmanuel Vadot hdlcd@2b000000 { 37*c66ec88fSEmmanuel Vadot compatible = "arm,hdlcd"; 38*c66ec88fSEmmanuel Vadot reg = <0 0x2b000000 0 0x1000>; 39*c66ec88fSEmmanuel Vadot interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 40*c66ec88fSEmmanuel Vadot clocks = <&oscclk5>; 41*c66ec88fSEmmanuel Vadot clock-names = "pxlclk"; 42*c66ec88fSEmmanuel Vadot port { 43*c66ec88fSEmmanuel Vadot hdlcd_output: endpoint@0 { 44*c66ec88fSEmmanuel Vadot remote-endpoint = <&hdmi_enc_input>; 45*c66ec88fSEmmanuel Vadot }; 46*c66ec88fSEmmanuel Vadot }; 47*c66ec88fSEmmanuel Vadot }; 48*c66ec88fSEmmanuel Vadot 49*c66ec88fSEmmanuel Vadot /* HDMI encoder on I2C bus */ 50*c66ec88fSEmmanuel Vadot i2c@7ffa0000 { 51*c66ec88fSEmmanuel Vadot .... 52*c66ec88fSEmmanuel Vadot hdmi-transmitter@70 { 53*c66ec88fSEmmanuel Vadot compatible = "....."; 54*c66ec88fSEmmanuel Vadot reg = <0x70>; 55*c66ec88fSEmmanuel Vadot port@0 { 56*c66ec88fSEmmanuel Vadot hdmi_enc_input: endpoint { 57*c66ec88fSEmmanuel Vadot remote-endpoint = <&hdlcd_output>; 58*c66ec88fSEmmanuel Vadot }; 59*c66ec88fSEmmanuel Vadot 60*c66ec88fSEmmanuel Vadot hdmi_enc_output: endpoint { 61*c66ec88fSEmmanuel Vadot remote-endpoint = <&hdmi_1_port>; 62*c66ec88fSEmmanuel Vadot }; 63*c66ec88fSEmmanuel Vadot }; 64*c66ec88fSEmmanuel Vadot }; 65*c66ec88fSEmmanuel Vadot 66*c66ec88fSEmmanuel Vadot }; 67*c66ec88fSEmmanuel Vadot 68*c66ec88fSEmmanuel Vadot hdmi1: connector@1 { 69*c66ec88fSEmmanuel Vadot compatible = "hdmi-connector"; 70*c66ec88fSEmmanuel Vadot type = "a"; 71*c66ec88fSEmmanuel Vadot port { 72*c66ec88fSEmmanuel Vadot hdmi_1_port: endpoint { 73*c66ec88fSEmmanuel Vadot remote-endpoint = <&hdmi_enc_output>; 74*c66ec88fSEmmanuel Vadot }; 75*c66ec88fSEmmanuel Vadot }; 76*c66ec88fSEmmanuel Vadot }; 77*c66ec88fSEmmanuel Vadot 78*c66ec88fSEmmanuel Vadot ... 79*c66ec88fSEmmanuel Vadot}; 80