xref: /freebsd/sys/contrib/device-tree/Bindings/display/amlogic,meson-vpu.yaml (revision 5def4c47d4bd90b209b9b4a4ba9faec15846d8fd) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Amlogic Meson Display Controller
9
10maintainers:
11  - Neil Armstrong <narmstrong@baylibre.com>
12
13description: |
14  The Amlogic Meson Display controller is composed of several components
15  that are going to be documented below
16
17  DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
18     | vd1   _______     _____________    _________________     |               |
19  D  |-------|      |----|            |   |                |    |   HDMI PLL    |
20  D  | vd2   | VIU  |    | Video Post |   | Video Encoders |<---|-----VCLK      |
21  R  |-------|      |----| Processing |   |                |    |               |
22     | osd2  |      |    |            |---| Enci ----------|----|-----VDAC------|
23  R  |-------| CSC  |----| Scalers    |   | Encp ----------|----|----HDMI-TX----|
24  A  | osd1  |      |    | Blenders   |   | Encl ----------|----|---------------|
25  M  |-------|______|----|____________|   |________________|    |               |
26  ___|__________________________________________________________|_______________|
27
28
29  VIU: Video Input Unit
30  ---------------------
31
32  The Video Input Unit is in charge of the pixel scanout from the DDR memory.
33  It fetches the frames addresses, stride and parameters from the "Canvas" memory.
34  This part is also in charge of the CSC (Colorspace Conversion).
35  It can handle 2 OSD Planes and 2 Video Planes.
36
37  VPP: Video Post Processing
38  --------------------------
39
40  The Video Post Processing is in charge of the scaling and blending of the
41  various planes into a single pixel stream.
42  There is a special "pre-blending" used by the video planes with a dedicated
43  scaler and a "post-blending" to merge with the OSD Planes.
44  The OSD planes also have a dedicated scaler for one of the OSD.
45
46  VENC: Video Encoders
47  --------------------
48
49  The VENC is composed of the multiple pixel encoders
50   - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
51   - ENCP : Progressive Video Encoder for HDMI
52   - ENCL : LCD LVDS Encoder
53  The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
54  tree and provides the scanout clock to the VPP and VIU.
55  The ENCI is connected to a single VDAC for Composite Output.
56  The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
57
58properties:
59  compatible:
60    oneOf:
61      - items:
62          - enum:
63              - amlogic,meson-gxbb-vpu # GXBB (S905)
64              - amlogic,meson-gxl-vpu # GXL (S905X, S905D)
65              - amlogic,meson-gxm-vpu # GXM (S912)
66          - const: amlogic,meson-gx-vpu
67      - enum:
68          - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
69
70  reg:
71    maxItems: 2
72
73  reg-names:
74    items:
75      - const: vpu
76      - const: hhi
77
78  interrupts:
79    maxItems: 1
80
81  power-domains:
82    maxItems: 1
83    description: phandle to the associated power domain
84
85  port@0:
86    $ref: /schemas/graph.yaml#/properties/port
87    description:
88      A port node pointing to the CVBS VDAC port node.
89
90  port@1:
91    $ref: /schemas/graph.yaml#/properties/port
92    description:
93      A port node pointing to the HDMI-TX port node.
94
95  "#address-cells":
96    const: 1
97
98  "#size-cells":
99    const: 0
100
101required:
102  - compatible
103  - reg
104  - interrupts
105  - port@0
106  - port@1
107  - "#address-cells"
108  - "#size-cells"
109
110additionalProperties: false
111
112examples:
113  - |
114    vpu: vpu@d0100000 {
115        compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
116        reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;
117        reg-names = "vpu", "hhi";
118        interrupts = <3>;
119        #address-cells = <1>;
120        #size-cells = <0>;
121
122        /* CVBS VDAC output port */
123        port@0 {
124            reg = <0>;
125
126            cvbs_vdac_out: endpoint {
127                remote-endpoint = <&tv_connector_in>;
128            };
129        };
130
131        /* HDMI TX output port */
132        port@1 {
133            reg = <1>;
134
135            hdmi_tx_out: endpoint {
136                remote-endpoint = <&hdmi_tx_in>;
137            };
138        };
139    };
140