xref: /freebsd/sys/contrib/device-tree/Bindings/display/amlogic,meson-g12a-dw-mipi-dsi.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2020 BayLibre, SAS
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
9
10maintainers:
11  - Neil Armstrong <neil.armstrong@linaro.org>
12
13description: |
14  The Amlogic Meson Synopsys Designware Integration is composed of
15  - A Synopsys DesignWare MIPI DSI Host Controller IP
16  - A TOP control block controlling the Clocks & Resets of the IP
17
18allOf:
19  - $ref: dsi-controller.yaml#
20
21properties:
22  compatible:
23    enum:
24      - amlogic,meson-g12a-dw-mipi-dsi
25
26  reg:
27    maxItems: 1
28
29  clocks:
30    minItems: 3
31    maxItems: 4
32
33  clock-names:
34    minItems: 3
35    items:
36      - const: pclk
37      - const: bit
38      - const: px
39      - const: meas
40
41  resets:
42    maxItems: 1
43
44  reset-names:
45    items:
46      - const: top
47
48  phys:
49    maxItems: 1
50
51  phy-names:
52    items:
53      - const: dphy
54
55  ports:
56    $ref: /schemas/graph.yaml#/properties/ports
57
58    properties:
59      port@0:
60        $ref: /schemas/graph.yaml#/properties/port
61        description: Input node to receive pixel data.
62
63      port@1:
64        $ref: /schemas/graph.yaml#/properties/port
65        description: DSI output node to panel.
66
67    required:
68      - port@0
69      - port@1
70
71required:
72  - compatible
73  - reg
74  - clocks
75  - clock-names
76  - resets
77  - reset-names
78  - phys
79  - phy-names
80  - ports
81
82unevaluatedProperties: false
83
84examples:
85  - |
86    dsi@6000 {
87          compatible = "amlogic,meson-g12a-dw-mipi-dsi";
88          reg = <0x6000 0x400>;
89          resets = <&reset_top>;
90          reset-names = "top";
91          clocks = <&clk_pclk>, <&bit_clk>, <&clk_px>;
92          clock-names = "pclk", "bit", "px";
93          phys = <&mipi_dphy>;
94          phy-names = "dphy";
95
96          ports {
97              #address-cells = <1>;
98              #size-cells = <0>;
99
100              /* VPU VENC Input */
101              mipi_dsi_venc_port: port@0 {
102                  reg = <0>;
103
104                  mipi_dsi_in: endpoint {
105                       remote-endpoint = <&dpi_out>;
106                  };
107              };
108
109              /* DSI Output */
110              mipi_dsi_panel_port: port@1 {
111                  reg = <1>;
112
113                  mipi_out_panel: endpoint {
114                      remote-endpoint = <&mipi_in_panel>;
115                  };
116              };
117          };
118    };
119