1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright 2019 BayLibre, SAS 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Amlogic specific extensions to the Synopsys Designware HDMI Controller 9 10maintainers: 11 - Neil Armstrong <neil.armstrong@linaro.org> 12 13allOf: 14 - $ref: /schemas/sound/dai-common.yaml# 15 16description: | 17 The Amlogic Meson Synopsys Designware Integration is composed of 18 - A Synopsys DesignWare HDMI Controller IP 19 - A TOP control block controlling the Clocks and PHY 20 - A custom HDMI PHY in order to convert video to TMDS signal 21 ___________________________________ 22 | HDMI TOP |<= HPD 23 |___________________________________| 24 | | | 25 | Synopsys HDMI | HDMI PHY |=> TMDS 26 | Controller |________________| 27 |___________________________________|<=> DDC 28 29 The HDMI TOP block only supports HPD sensing. 30 The Synopsys HDMI Controller interrupt is routed through the 31 TOP Block interrupt. 32 Communication to the TOP Block and the Synopsys HDMI Controller is done 33 via a pair of dedicated addr+read/write registers. 34 The HDMI PHY is configured by registers in the HHI register block. 35 36 Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux 37 selects either the ENCI encoder for the 576i or 480i formats or the ENCP 38 encoder for all the other formats including interlaced HD formats. 39 40 The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate 41 DVI timings for the HDMI controller. 42 43 Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare 44 HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF 45 audio source interfaces. 46 47properties: 48 compatible: 49 oneOf: 50 - items: 51 - enum: 52 - amlogic,meson-gxbb-dw-hdmi # GXBB (S905) 53 - amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D) 54 - amlogic,meson-gxm-dw-hdmi # GXM (S912) 55 - const: amlogic,meson-gx-dw-hdmi 56 - enum: 57 - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2) 58 59 reg: 60 maxItems: 1 61 62 interrupts: 63 maxItems: 1 64 65 clocks: 66 minItems: 3 67 68 clock-names: 69 items: 70 - const: isfr 71 - const: iahb 72 - const: venci 73 74 resets: 75 minItems: 3 76 77 reset-names: 78 items: 79 - const: hdmitx_apb 80 - const: hdmitx 81 - const: hdmitx_phy 82 83 hdmi-supply: 84 description: phandle to an external 5V regulator to power the HDMI logic 85 86 port@0: 87 $ref: /schemas/graph.yaml#/properties/port 88 description: 89 A port node pointing to the VENC Input port node. 90 91 port@1: 92 $ref: /schemas/graph.yaml#/properties/port 93 description: 94 A port node pointing to the TMDS Output port node. 95 96 "#address-cells": 97 const: 1 98 99 "#size-cells": 100 const: 0 101 102 "#sound-dai-cells": 103 const: 0 104 105 sound-name-prefix: true 106 107required: 108 - compatible 109 - reg 110 - interrupts 111 - clocks 112 - clock-names 113 - resets 114 - reset-names 115 - port@0 116 - port@1 117 - "#address-cells" 118 - "#size-cells" 119 120additionalProperties: false 121 122examples: 123 - | 124 hdmi_tx: hdmi-tx@c883a000 { 125 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; 126 reg = <0xc883a000 0x1c>; 127 interrupts = <57>; 128 resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>; 129 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 130 clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>; 131 clock-names = "isfr", "iahb", "venci"; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 135 /* VPU VENC Input */ 136 hdmi_tx_venc_port: port@0 { 137 reg = <0>; 138 139 hdmi_tx_in: endpoint { 140 remote-endpoint = <&hdmi_tx_out>; 141 }; 142 }; 143 144 /* TMDS Output */ 145 hdmi_tx_tmds_port: port@1 { 146 reg = <1>; 147 148 hdmi_tx_tmds_out: endpoint { 149 remote-endpoint = <&hdmi_connector_in>; 150 }; 151 }; 152 }; 153