xref: /freebsd/sys/contrib/device-tree/Bindings/display/amlogic,meson-dw-hdmi.yaml (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
9
10maintainers:
11  - Neil Armstrong <narmstrong@baylibre.com>
12
13description: |
14  The Amlogic Meson Synopsys Designware Integration is composed of
15  - A Synopsys DesignWare HDMI Controller IP
16  - A TOP control block controlling the Clocks and PHY
17  - A custom HDMI PHY in order to convert video to TMDS signal
18   ___________________________________
19  |            HDMI TOP               |<= HPD
20  |___________________________________|
21  |                  |                |
22  |  Synopsys HDMI   |   HDMI PHY     |=> TMDS
23  |    Controller    |________________|
24  |___________________________________|<=> DDC
25
26  The HDMI TOP block only supports HPD sensing.
27  The Synopsys HDMI Controller interrupt is routed through the
28  TOP Block interrupt.
29  Communication to the TOP Block and the Synopsys HDMI Controller is done
30  via a pair of dedicated addr+read/write registers.
31  The HDMI PHY is configured by registers in the HHI register block.
32
33  Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux
34  selects either the ENCI encoder for the 576i or 480i formats or the ENCP
35  encoder for all the other formats including interlaced HD formats.
36
37  The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
38  DVI timings for the HDMI controller.
39
40  Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
41  HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
42  audio source interfaces.
43
44properties:
45  compatible:
46    oneOf:
47      - items:
48          - enum:
49              - amlogic,meson-gxbb-dw-hdmi # GXBB (S905)
50              - amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D)
51              - amlogic,meson-gxm-dw-hdmi # GXM (S912)
52          - const: amlogic,meson-gx-dw-hdmi
53      - enum:
54          - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
55
56  reg:
57    maxItems: 1
58
59  interrupts:
60    maxItems: 1
61
62  clocks:
63    minItems: 3
64
65  clock-names:
66    items:
67      - const: isfr
68      - const: iahb
69      - const: venci
70
71  resets:
72    minItems: 3
73
74  reset-names:
75    items:
76      - const: hdmitx_apb
77      - const: hdmitx
78      - const: hdmitx_phy
79
80  hdmi-supply:
81    description: phandle to an external 5V regulator to power the HDMI logic
82
83  port@0:
84    type: object
85    description:
86      A port node pointing to the VENC Input port node.
87
88  port@1:
89    type: object
90    description:
91      A port node pointing to the TMDS Output port node.
92
93  "#address-cells":
94    const: 1
95
96  "#size-cells":
97    const: 0
98
99  "#sound-dai-cells":
100    const: 0
101
102required:
103  - compatible
104  - reg
105  - interrupts
106  - clocks
107  - clock-names
108  - resets
109  - reset-names
110  - port@0
111  - port@1
112  - "#address-cells"
113  - "#size-cells"
114
115additionalProperties: false
116
117examples:
118  - |
119    hdmi_tx: hdmi-tx@c883a000 {
120        compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
121        reg = <0xc883a000 0x1c>;
122        interrupts = <57>;
123        resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>;
124        reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
125        clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>;
126        clock-names = "isfr", "iahb", "venci";
127        #address-cells = <1>;
128        #size-cells = <0>;
129
130        /* VPU VENC Input */
131        hdmi_tx_venc_port: port@0 {
132            reg = <0>;
133
134            hdmi_tx_in: endpoint {
135                remote-endpoint = <&hdmi_tx_out>;
136            };
137        };
138
139        /* TMDS Output */
140        hdmi_tx_tmds_port: port@1 {
141             reg = <1>;
142
143             hdmi_tx_tmds_out: endpoint {
144                 remote-endpoint = <&hdmi_connector_in>;
145             };
146        };
147    };
148
149