1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner R40 TCON TOP Device Tree Bindings 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13description: | 14 TCON TOPs main purpose is to configure whole display pipeline. It 15 determines relationships between mixers and TCONs, selects source 16 TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV 17 encoder clock source and contains additional TV TCON and DSI gates. 18 19 It allows display pipeline to be configured in very different ways: 20 21 / LCD0/LVDS0 22 / [0] TCON-LCD0 23 | \ MIPI DSI 24 mixer0 | 25 \ / [1] TCON-LCD1 - LCD1/LVDS1 26 TCON-TOP 27 / \ [2] TCON-TV0 [0] - TVE0/RGB 28 mixer1 | \ 29 | TCON-TOP - HDMI 30 | / 31 \ [3] TCON-TV1 [1] - TVE1/RGB 32 33 Note that both TCON TOP references same physical unit. Both mixers 34 can be connected to any TCON. Not all TCON TOP variants support all 35 features. 36 37properties: 38 "#clock-cells": 39 const: 1 40 41 compatible: 42 enum: 43 - allwinner,sun8i-r40-tcon-top 44 - allwinner,sun50i-h6-tcon-top 45 46 reg: 47 maxItems: 1 48 49 clocks: 50 minItems: 2 51 maxItems: 6 52 items: 53 - description: The TCON TOP interface clock 54 - description: The TCON TOP TV0 clock 55 - description: The TCON TOP TVE0 clock 56 - description: The TCON TOP TV1 clock 57 - description: The TCON TOP TVE1 clock 58 - description: The TCON TOP MIPI DSI clock 59 60 clock-names: 61 minItems: 2 62 maxItems: 6 63 items: 64 - const: bus 65 - const: tcon-tv0 66 - const: tve0 67 - const: tcon-tv1 68 - const: tve1 69 - const: dsi 70 71 clock-output-names: 72 minItems: 1 73 maxItems: 3 74 description: > 75 The first item is the name of the clock created for the TV0 76 channel, the second item is the name of the TCON TV1 channel 77 clock and the third one is the name of the DSI channel clock. 78 79 resets: 80 maxItems: 1 81 82 ports: 83 $ref: /schemas/graph.yaml#/properties/ports 84 85 properties: 86 port@0: 87 $ref: /schemas/graph.yaml#/properties/port 88 description: | 89 Input endpoint for Mixer 0 mux. 90 91 port@1: 92 $ref: /schemas/graph.yaml#/properties/port 93 description: | 94 Output endpoint for Mixer 0 mux 95 96 port@2: 97 $ref: /schemas/graph.yaml#/properties/port 98 description: | 99 Input endpoint for Mixer 1 mux. 100 101 port@3: 102 $ref: /schemas/graph.yaml#/properties/port 103 description: | 104 Output endpoint for Mixer 1 mux 105 106 port@4: 107 $ref: /schemas/graph.yaml#/properties/port 108 description: | 109 Input endpoint for HDMI mux. 110 111 port@5: 112 $ref: /schemas/graph.yaml#/properties/port 113 description: | 114 Output endpoint for HDMI mux 115 116 required: 117 - port@0 118 - port@1 119 - port@4 120 - port@5 121 122required: 123 - "#clock-cells" 124 - compatible 125 - reg 126 - clocks 127 - clock-names 128 - clock-output-names 129 - resets 130 - ports 131 132additionalProperties: false 133 134if: 135 properties: 136 compatible: 137 contains: 138 const: allwinner,sun50i-h6-tcon-top 139 140then: 141 properties: 142 clocks: 143 maxItems: 2 144 145 clock-output-names: 146 maxItems: 1 147 148else: 149 properties: 150 clocks: 151 minItems: 6 152 153 clock-output-names: 154 minItems: 3 155 156 ports: 157 required: 158 - port@2 159 - port@3 160 161examples: 162 - | 163 #include <dt-bindings/interrupt-controller/arm-gic.h> 164 165 #include <dt-bindings/clock/sun8i-r40-ccu.h> 166 #include <dt-bindings/reset/sun8i-r40-ccu.h> 167 168 tcon_top: tcon-top@1c70000 { 169 compatible = "allwinner,sun8i-r40-tcon-top"; 170 reg = <0x01c70000 0x1000>; 171 clocks = <&ccu CLK_BUS_TCON_TOP>, 172 <&ccu CLK_TCON_TV0>, 173 <&ccu CLK_TVE0>, 174 <&ccu CLK_TCON_TV1>, 175 <&ccu CLK_TVE1>, 176 <&ccu CLK_DSI_DPHY>; 177 clock-names = "bus", 178 "tcon-tv0", 179 "tve0", 180 "tcon-tv1", 181 "tve1", 182 "dsi"; 183 clock-output-names = "tcon-top-tv0", 184 "tcon-top-tv1", 185 "tcon-top-dsi"; 186 resets = <&ccu RST_BUS_TCON_TOP>; 187 #clock-cells = <1>; 188 189 ports { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 tcon_top_mixer0_in: port@0 { 194 reg = <0>; 195 196 tcon_top_mixer0_in_mixer0: endpoint { 197 remote-endpoint = <&mixer0_out_tcon_top>; 198 }; 199 }; 200 201 tcon_top_mixer0_out: port@1 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 reg = <1>; 205 206 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 207 reg = <0>; 208 }; 209 210 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { 211 reg = <1>; 212 }; 213 214 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 215 reg = <2>; 216 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 217 }; 218 219 tcon_top_mixer0_out_tcon_tv1: endpoint@3 { 220 reg = <3>; 221 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; 222 }; 223 }; 224 225 tcon_top_mixer1_in: port@2 { 226 #address-cells = <1>; 227 #size-cells = <0>; 228 reg = <2>; 229 230 tcon_top_mixer1_in_mixer1: endpoint@1 { 231 reg = <1>; 232 remote-endpoint = <&mixer1_out_tcon_top>; 233 }; 234 }; 235 236 tcon_top_mixer1_out: port@3 { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 reg = <3>; 240 241 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 242 reg = <0>; 243 }; 244 245 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { 246 reg = <1>; 247 }; 248 249 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 250 reg = <2>; 251 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 252 }; 253 254 tcon_top_mixer1_out_tcon_tv1: endpoint@3 { 255 reg = <3>; 256 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; 257 }; 258 }; 259 260 tcon_top_hdmi_in: port@4 { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 reg = <4>; 264 265 tcon_top_hdmi_in_tcon_tv0: endpoint@0 { 266 reg = <0>; 267 remote-endpoint = <&tcon_tv0_out_tcon_top>; 268 }; 269 270 tcon_top_hdmi_in_tcon_tv1: endpoint@1 { 271 reg = <1>; 272 remote-endpoint = <&tcon_tv1_out_tcon_top>; 273 }; 274 }; 275 276 tcon_top_hdmi_out: port@5 { 277 reg = <5>; 278 279 tcon_top_hdmi_out_hdmi: endpoint { 280 remote-endpoint = <&hdmi_in_tcon_top>; 281 }; 282 }; 283 }; 284 }; 285 286... 287