1* Generic Exynos Bus frequency device 2 3The Samsung Exynos SoC has many buses for data transfer between DRAM 4and sub-blocks in SoC. Most Exynos SoCs share the common architecture 5for buses. Generally, each bus of Exynos SoC includes a source clock 6and a power line, which are able to change the clock frequency 7of the bus in runtime. To monitor the usage of each bus in runtime, 8the driver uses the PPMU (Platform Performance Monitoring Unit), which 9is able to measure the current load of sub-blocks. 10 11The Exynos SoC includes the various sub-blocks which have the each AXI bus. 12The each AXI bus has the owned source clock but, has not the only owned 13power line. The power line might be shared among one more sub-blocks. 14So, we can divide into two type of device as the role of each sub-block. 15There are two type of bus devices as following: 16- parent bus device 17- passive bus device 18 19Basically, parent and passive bus device share the same power line. 20The parent bus device can only change the voltage of shared power line 21and the rest bus devices (passive bus device) depend on the decision of 22the parent bus device. If there are three blocks which share the VDD_xxx 23power line, Only one block should be parent device and then the rest blocks 24should depend on the parent device as passive device. 25 26 VDD_xxx |--- A block (parent) 27 |--- B block (passive) 28 |--- C block (passive) 29 30There are a little different composition among Exynos SoC because each Exynos 31SoC has different sub-blocks. Therefore, such difference should be specified 32in devicetree file instead of each device driver. In result, this driver 33is able to support the bus frequency for all Exynos SoCs. 34 35Required properties for all bus devices: 36- compatible: Should be "samsung,exynos-bus". 37- clock-names : the name of clock used by the bus, "bus". 38- clocks : phandles for clock specified in "clock-names" property. 39- operating-points-v2: the OPP table including frequency/voltage information 40 to support DVFS (Dynamic Voltage/Frequency Scaling) feature. 41 42Required properties only for parent bus device: 43- vdd-supply: the regulator to provide the buses with the voltage. 44- devfreq-events: the devfreq-event device to monitor the current utilization 45 of buses. 46 47Required properties only for passive bus device: 48- devfreq: the parent bus device. 49 50Optional properties only for parent bus device: 51- exynos,saturation-ratio: the percentage value which is used to calibrate 52 the performance count against total cycle count. 53 54Detailed correlation between sub-blocks and power line according to Exynos SoC: 55- In case of Exynos3250, there are two power line as following: 56 VDD_MIF |--- DMC 57 58 VDD_INT |--- LEFTBUS (parent device) 59 |--- PERIL 60 |--- MFC 61 |--- G3D 62 |--- RIGHTBUS 63 |--- PERIR 64 |--- FSYS 65 |--- LCD0 66 |--- PERIR 67 |--- ISP 68 |--- CAM 69 70- In case of Exynos4210, there is one power line as following: 71 VDD_INT |--- DMC (parent device) 72 |--- LEFTBUS 73 |--- PERIL 74 |--- MFC(L) 75 |--- G3D 76 |--- TV 77 |--- LCD0 78 |--- RIGHTBUS 79 |--- PERIR 80 |--- MFC(R) 81 |--- CAM 82 |--- FSYS 83 |--- GPS 84 |--- LCD0 85 |--- LCD1 86 87- In case of Exynos4x12, there are two power line as following: 88 VDD_MIF |--- DMC 89 90 VDD_INT |--- LEFTBUS (parent device) 91 |--- PERIL 92 |--- MFC(L) 93 |--- G3D 94 |--- TV 95 |--- IMAGE 96 |--- RIGHTBUS 97 |--- PERIR 98 |--- MFC(R) 99 |--- CAM 100 |--- FSYS 101 |--- GPS 102 |--- LCD0 103 |--- ISP 104 105- In case of Exynos5422, there are two power line as following: 106 VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller) 107 |--- DREX 1 108 109 VDD_INT |--- NoC_Core (parent device) 110 |--- G2D 111 |--- G3D 112 |--- DISP1 113 |--- NoC_WCORE 114 |--- GSCL 115 |--- MSCL 116 |--- ISP 117 |--- MFC 118 |--- GEN 119 |--- PERIS 120 |--- PERIC 121 |--- FSYS 122 |--- FSYS2 123 124- In case of Exynos5433, there is VDD_INT power line as following: 125 VDD_INT |--- G2D (parent device) 126 |--- MSCL 127 |--- GSCL 128 |--- JPEG 129 |--- MFC 130 |--- HEVC 131 |--- BUS0 132 |--- BUS1 133 |--- BUS2 134 |--- PERIS (Fixed clock rate) 135 |--- PERIC (Fixed clock rate) 136 |--- FSYS (Fixed clock rate) 137 138Example1: 139 Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to 140 power line (regulator). The MIF (Memory Interface) AXI bus is used to 141 transfer data between DRAM and CPU and uses the VDD_MIF regulator. 142 143 - MIF (Memory Interface) block 144 : VDD_MIF |--- DMC (Dynamic Memory Controller) 145 146 - INT (Internal) block 147 : VDD_INT |--- LEFTBUS (parent device) 148 |--- PERIL 149 |--- MFC 150 |--- G3D 151 |--- RIGHTBUS 152 |--- FSYS 153 |--- LCD0 154 |--- PERIR 155 |--- ISP 156 |--- CAM 157 158 - MIF bus's frequency/voltage table 159 ----------------------- 160 |Lv| Freq | Voltage | 161 ----------------------- 162 |L1| 50000 |800000 | 163 |L2| 100000 |800000 | 164 |L3| 134000 |800000 | 165 |L4| 200000 |825000 | 166 |L5| 400000 |875000 | 167 ----------------------- 168 169 - INT bus's frequency/voltage table 170 ---------------------------------------------------------- 171 |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT | 172 | name| |LCD0 | | | || | 173 | | |FSYS | | | || | 174 | | |MFC | | | || | 175 ---------------------------------------------------------- 176 |Mode |*parent|passive |passive|passive|passive|| | 177 ---------------------------------------------------------- 178 |Lv |Frequency ||Voltage | 179 ---------------------------------------------------------- 180 |L1 |50000 |50000 |50000 |50000 |50000 ||900000 | 181 |L2 |80000 |80000 |80000 |80000 |80000 ||900000 | 182 |L3 |100000 |100000 |100000 |100000 |100000 ||1000000 | 183 |L4 |134000 |134000 |200000 |200000 | ||1000000 | 184 |L5 |200000 |200000 |400000 |300000 | ||1000000 | 185 ---------------------------------------------------------- 186 187Example2 : 188 The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi 189 is listed below: 190 191 bus_dmc: bus_dmc { 192 compatible = "samsung,exynos-bus"; 193 clocks = <&cmu_dmc CLK_DIV_DMC>; 194 clock-names = "bus"; 195 operating-points-v2 = <&bus_dmc_opp_table>; 196 status = "disabled"; 197 }; 198 199 bus_dmc_opp_table: opp_table1 { 200 compatible = "operating-points-v2"; 201 opp-shared; 202 203 opp-50000000 { 204 opp-hz = /bits/ 64 <50000000>; 205 opp-microvolt = <800000>; 206 }; 207 opp-100000000 { 208 opp-hz = /bits/ 64 <100000000>; 209 opp-microvolt = <800000>; 210 }; 211 opp-134000000 { 212 opp-hz = /bits/ 64 <134000000>; 213 opp-microvolt = <800000>; 214 }; 215 opp-200000000 { 216 opp-hz = /bits/ 64 <200000000>; 217 opp-microvolt = <825000>; 218 }; 219 opp-400000000 { 220 opp-hz = /bits/ 64 <400000000>; 221 opp-microvolt = <875000>; 222 }; 223 }; 224 225 bus_leftbus: bus_leftbus { 226 compatible = "samsung,exynos-bus"; 227 clocks = <&cmu CLK_DIV_GDL>; 228 clock-names = "bus"; 229 operating-points-v2 = <&bus_leftbus_opp_table>; 230 status = "disabled"; 231 }; 232 233 bus_rightbus: bus_rightbus { 234 compatible = "samsung,exynos-bus"; 235 clocks = <&cmu CLK_DIV_GDR>; 236 clock-names = "bus"; 237 operating-points-v2 = <&bus_leftbus_opp_table>; 238 status = "disabled"; 239 }; 240 241 bus_lcd0: bus_lcd0 { 242 compatible = "samsung,exynos-bus"; 243 clocks = <&cmu CLK_DIV_ACLK_160>; 244 clock-names = "bus"; 245 operating-points-v2 = <&bus_leftbus_opp_table>; 246 status = "disabled"; 247 }; 248 249 bus_fsys: bus_fsys { 250 compatible = "samsung,exynos-bus"; 251 clocks = <&cmu CLK_DIV_ACLK_200>; 252 clock-names = "bus"; 253 operating-points-v2 = <&bus_leftbus_opp_table>; 254 status = "disabled"; 255 }; 256 257 bus_mcuisp: bus_mcuisp { 258 compatible = "samsung,exynos-bus"; 259 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; 260 clock-names = "bus"; 261 operating-points-v2 = <&bus_mcuisp_opp_table>; 262 status = "disabled"; 263 }; 264 265 bus_isp: bus_isp { 266 compatible = "samsung,exynos-bus"; 267 clocks = <&cmu CLK_DIV_ACLK_266>; 268 clock-names = "bus"; 269 operating-points-v2 = <&bus_isp_opp_table>; 270 status = "disabled"; 271 }; 272 273 bus_peril: bus_peril { 274 compatible = "samsung,exynos-bus"; 275 clocks = <&cmu CLK_DIV_ACLK_100>; 276 clock-names = "bus"; 277 operating-points-v2 = <&bus_peril_opp_table>; 278 status = "disabled"; 279 }; 280 281 bus_mfc: bus_mfc { 282 compatible = "samsung,exynos-bus"; 283 clocks = <&cmu CLK_SCLK_MFC>; 284 clock-names = "bus"; 285 operating-points-v2 = <&bus_leftbus_opp_table>; 286 status = "disabled"; 287 }; 288 289 bus_leftbus_opp_table: opp_table1 { 290 compatible = "operating-points-v2"; 291 opp-shared; 292 293 opp-50000000 { 294 opp-hz = /bits/ 64 <50000000>; 295 opp-microvolt = <900000>; 296 }; 297 opp-80000000 { 298 opp-hz = /bits/ 64 <80000000>; 299 opp-microvolt = <900000>; 300 }; 301 opp-100000000 { 302 opp-hz = /bits/ 64 <100000000>; 303 opp-microvolt = <1000000>; 304 }; 305 opp-134000000 { 306 opp-hz = /bits/ 64 <134000000>; 307 opp-microvolt = <1000000>; 308 }; 309 opp-200000000 { 310 opp-hz = /bits/ 64 <200000000>; 311 opp-microvolt = <1000000>; 312 }; 313 }; 314 315 bus_mcuisp_opp_table: opp_table2 { 316 compatible = "operating-points-v2"; 317 opp-shared; 318 319 opp-50000000 { 320 opp-hz = /bits/ 64 <50000000>; 321 }; 322 opp-80000000 { 323 opp-hz = /bits/ 64 <80000000>; 324 }; 325 opp-100000000 { 326 opp-hz = /bits/ 64 <100000000>; 327 }; 328 opp-200000000 { 329 opp-hz = /bits/ 64 <200000000>; 330 }; 331 opp-400000000 { 332 opp-hz = /bits/ 64 <400000000>; 333 }; 334 }; 335 336 bus_isp_opp_table: opp_table3 { 337 compatible = "operating-points-v2"; 338 opp-shared; 339 340 opp-50000000 { 341 opp-hz = /bits/ 64 <50000000>; 342 }; 343 opp-80000000 { 344 opp-hz = /bits/ 64 <80000000>; 345 }; 346 opp-100000000 { 347 opp-hz = /bits/ 64 <100000000>; 348 }; 349 opp-200000000 { 350 opp-hz = /bits/ 64 <200000000>; 351 }; 352 opp-300000000 { 353 opp-hz = /bits/ 64 <300000000>; 354 }; 355 }; 356 357 bus_peril_opp_table: opp_table4 { 358 compatible = "operating-points-v2"; 359 opp-shared; 360 361 opp-50000000 { 362 opp-hz = /bits/ 64 <50000000>; 363 }; 364 opp-80000000 { 365 opp-hz = /bits/ 64 <80000000>; 366 }; 367 opp-100000000 { 368 opp-hz = /bits/ 64 <100000000>; 369 }; 370 }; 371 372 373 Usage case to handle the frequency and voltage of bus on runtime 374 in exynos3250-rinato.dts is listed below: 375 376 &bus_dmc { 377 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; 378 vdd-supply = <&buck1_reg>; /* VDD_MIF */ 379 status = "okay"; 380 }; 381 382 &bus_leftbus { 383 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; 384 vdd-supply = <&buck3_reg>; 385 status = "okay"; 386 }; 387 388 &bus_rightbus { 389 devfreq = <&bus_leftbus>; 390 status = "okay"; 391 }; 392 393 &bus_lcd0 { 394 devfreq = <&bus_leftbus>; 395 status = "okay"; 396 }; 397 398 &bus_fsys { 399 devfreq = <&bus_leftbus>; 400 status = "okay"; 401 }; 402 403 &bus_mcuisp { 404 devfreq = <&bus_leftbus>; 405 status = "okay"; 406 }; 407 408 &bus_isp { 409 devfreq = <&bus_leftbus>; 410 status = "okay"; 411 }; 412 413 &bus_peril { 414 devfreq = <&bus_leftbus>; 415 status = "okay"; 416 }; 417 418 &bus_mfc { 419 devfreq = <&bus_leftbus>; 420 status = "okay"; 421 }; 422