xref: /freebsd/sys/contrib/device-tree/Bindings/crypto/qcom-qce.yaml (revision 525fe93dc7487a1e63a90f6a2b956abc601963c1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm crypto engine driver
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  This document defines the binding for the QCE crypto
14  controller found on Qualcomm parts.
15
16properties:
17  compatible:
18    oneOf:
19      - const: qcom,crypto-v5.1
20        deprecated: true
21        description: Kept only for ABI backward compatibility
22
23      - const: qcom,crypto-v5.4
24        deprecated: true
25        description: Kept only for ABI backward compatibility
26
27      - items:
28          - enum:
29              - qcom,ipq6018-qce
30              - qcom,ipq8074-qce
31              - qcom,msm8996-qce
32              - qcom,sdm845-qce
33          - const: qcom,ipq4019-qce
34          - const: qcom,qce
35
36      - items:
37          - enum:
38              - qcom,sm8250-qce
39              - qcom,sm8350-qce
40              - qcom,sm8450-qce
41              - qcom,sm8550-qce
42          - const: qcom,sm8150-qce
43          - const: qcom,qce
44
45  reg:
46    maxItems: 1
47
48  clocks:
49    items:
50      - description: iface clocks register interface.
51      - description: bus clocks data transfer interface.
52      - description: core clocks rest of the crypto block.
53
54  clock-names:
55    items:
56      - const: iface
57      - const: bus
58      - const: core
59
60  iommus:
61    minItems: 1
62    maxItems: 8
63    description:
64      phandle to apps_smmu node with sid mask.
65
66  interconnects:
67    maxItems: 1
68    description:
69      Interconnect path between qce crypto and main memory.
70
71  interconnect-names:
72    const: memory
73
74  dmas:
75    items:
76      - description: DMA specifiers for rx dma channel.
77      - description: DMA specifiers for tx dma channel.
78
79  dma-names:
80    items:
81      - const: rx
82      - const: tx
83
84allOf:
85  - if:
86      properties:
87        compatible:
88          contains:
89            enum:
90              - qcom,crypto-v5.1
91              - qcom,crypto-v5.4
92              - qcom,ipq4019-qce
93
94    then:
95      required:
96        - clocks
97        - clock-names
98
99required:
100  - compatible
101  - reg
102  - dmas
103  - dma-names
104
105additionalProperties: false
106
107examples:
108  - |
109    #include <dt-bindings/clock/qcom,gcc-apq8084.h>
110    crypto-engine@fd45a000 {
111        compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";
112        reg = <0xfd45a000 0x6000>;
113        clocks = <&gcc GCC_CE2_AHB_CLK>,
114                 <&gcc GCC_CE2_AXI_CLK>,
115                 <&gcc GCC_CE2_CLK>;
116        clock-names = "iface", "bus", "core";
117        dmas = <&cryptobam 2>, <&cryptobam 3>;
118        dma-names = "rx", "tx";
119        iommus = <&apps_smmu 0x584 0x0011>,
120                 <&apps_smmu 0x586 0x0011>,
121                 <&apps_smmu 0x594 0x0011>,
122                 <&apps_smmu 0x596 0x0011>;
123    };
124