1Inside Secure SafeXcel cryptographic engine 2 3Required properties: 4- compatible: Should be "inside-secure,safexcel-eip197b", 5 "inside-secure,safexcel-eip197d" or 6 "inside-secure,safexcel-eip97ies". 7- reg: Base physical address of the engine and length of memory mapped region. 8- interrupts: Interrupt numbers for the rings and engine. 9- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem". 10 11Optional properties: 12- clocks: Reference to the crypto engine clocks, the second clock is 13 needed for the Armada 7K/8K SoCs. 14- clock-names: mandatory if there is a second clock, in this case the 15 name must be "core" for the first clock and "reg" for 16 the second one. 17 18Backward compatibility: 19Two compatibles are kept for backward compatibility, but shouldn't be used for 20new submissions: 21- "inside-secure,safexcel-eip197" is equivalent to 22 "inside-secure,safexcel-eip197b". 23- "inside-secure,safexcel-eip97" is equivalent to 24 "inside-secure,safexcel-eip97ies". 25 26Example: 27 28 crypto: crypto@800000 { 29 compatible = "inside-secure,safexcel-eip197b"; 30 reg = <0x800000 0x200000>; 31 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 37 interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", 38 "eip"; 39 clocks = <&cpm_syscon0 1 26>; 40 }; 41