1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings 8 9maintainers: 10 - Ilia Lin <ilia.lin@kernel.org> 11 12description: | 13 In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply 14 voltage is dynamically configured by Core Power Reduction (CPR) depending on 15 current CPU frequency and efuse values. 16 CPR provides a power domain with multiple levels that are selected depending 17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level 18 according to the required OPPs defined in the CPU OPP tables. 19 20select: 21 properties: 22 compatible: 23 contains: 24 enum: 25 - qcom,apq8064 26 - qcom,apq8096 27 - qcom,ipq8064 28 - qcom,msm8939 29 - qcom,msm8960 30 - qcom,msm8974 31 - qcom,msm8996 32 - qcom,qcs404 33 required: 34 - compatible 35 36properties: 37 cpus: 38 type: object 39 40 patternProperties: 41 'cpu@[0-9a-f]+': 42 type: object 43 44 properties: 45 power-domains: 46 maxItems: 1 47 48 power-domain-names: 49 items: 50 - const: cpr 51 52 required: 53 - power-domains 54 - power-domain-names 55 56patternProperties: 57 '^opp-table(-[a-z0-9]+)?$': 58 if: 59 properties: 60 compatible: 61 const: operating-points-v2-kryo-cpu 62 then: 63 patternProperties: 64 '^opp-?[0-9]+$': 65 required: 66 - required-opps 67 68additionalProperties: true 69 70examples: 71 - | 72 / { 73 model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; 74 compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404"; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 78 cpus { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 82 CPU0: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x100>; 86 enable-method = "psci"; 87 cpu-idle-states = <&CPU_SLEEP_0>; 88 next-level-cache = <&L2_0>; 89 #cooling-cells = <2>; 90 clocks = <&apcs_glb>; 91 operating-points-v2 = <&cpu_opp_table>; 92 power-domains = <&cpr>; 93 power-domain-names = "cpr"; 94 }; 95 96 CPU1: cpu@101 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x101>; 100 enable-method = "psci"; 101 cpu-idle-states = <&CPU_SLEEP_0>; 102 next-level-cache = <&L2_0>; 103 #cooling-cells = <2>; 104 clocks = <&apcs_glb>; 105 operating-points-v2 = <&cpu_opp_table>; 106 power-domains = <&cpr>; 107 power-domain-names = "cpr"; 108 }; 109 110 CPU2: cpu@102 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a53"; 113 reg = <0x102>; 114 enable-method = "psci"; 115 cpu-idle-states = <&CPU_SLEEP_0>; 116 next-level-cache = <&L2_0>; 117 #cooling-cells = <2>; 118 clocks = <&apcs_glb>; 119 operating-points-v2 = <&cpu_opp_table>; 120 power-domains = <&cpr>; 121 power-domain-names = "cpr"; 122 }; 123 124 CPU3: cpu@103 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a53"; 127 reg = <0x103>; 128 enable-method = "psci"; 129 cpu-idle-states = <&CPU_SLEEP_0>; 130 next-level-cache = <&L2_0>; 131 #cooling-cells = <2>; 132 clocks = <&apcs_glb>; 133 operating-points-v2 = <&cpu_opp_table>; 134 power-domains = <&cpr>; 135 power-domain-names = "cpr"; 136 }; 137 }; 138 139 cpu_opp_table: opp-table-cpu { 140 compatible = "operating-points-v2-kryo-cpu"; 141 opp-shared; 142 143 opp-1094400000 { 144 opp-hz = /bits/ 64 <1094400000>; 145 required-opps = <&cpr_opp1>; 146 }; 147 opp-1248000000 { 148 opp-hz = /bits/ 64 <1248000000>; 149 required-opps = <&cpr_opp2>; 150 }; 151 opp-1401600000 { 152 opp-hz = /bits/ 64 <1401600000>; 153 required-opps = <&cpr_opp3>; 154 }; 155 }; 156 157 cpr_opp_table: opp-table-cpr { 158 compatible = "operating-points-v2-qcom-level"; 159 160 cpr_opp1: opp1 { 161 opp-level = <1>; 162 qcom,opp-fuse-level = <1>; 163 }; 164 cpr_opp2: opp2 { 165 opp-level = <2>; 166 qcom,opp-fuse-level = <2>; 167 }; 168 cpr_opp3: opp3 { 169 opp-level = <3>; 170 qcom,opp-fuse-level = <3>; 171 }; 172 }; 173 }; 174