1c66ec88fSEmmanuel VadotBinding for NVIDIA Tegra20 CPUFreq 2c66ec88fSEmmanuel Vadot================================== 3c66ec88fSEmmanuel Vadot 4c66ec88fSEmmanuel VadotRequired properties: 5c66ec88fSEmmanuel Vadot- clocks: Must contain an entry for the CPU clock. 6c66ec88fSEmmanuel Vadot See ../clocks/clock-bindings.txt for details. 7*354d7675SEmmanuel Vadot- operating-points-v2: See ../bindings/opp/opp-v2.yaml for details. 8c66ec88fSEmmanuel Vadot- #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details. 9c66ec88fSEmmanuel Vadot 10c66ec88fSEmmanuel VadotFor each opp entry in 'operating-points-v2' table: 11c66ec88fSEmmanuel Vadot- opp-supported-hw: Two bitfields indicating: 12c66ec88fSEmmanuel Vadot On Tegra20: 13c66ec88fSEmmanuel Vadot 1. CPU process ID mask 14c66ec88fSEmmanuel Vadot 2. SoC speedo ID mask 15c66ec88fSEmmanuel Vadot 16c66ec88fSEmmanuel Vadot On Tegra30: 17c66ec88fSEmmanuel Vadot 1. CPU process ID mask 18c66ec88fSEmmanuel Vadot 2. CPU speedo ID mask 19c66ec88fSEmmanuel Vadot 20c66ec88fSEmmanuel Vadot A bitwise AND is performed against these values and if any bit 21c66ec88fSEmmanuel Vadot matches, the OPP gets enabled. 22c66ec88fSEmmanuel Vadot 23c66ec88fSEmmanuel Vadot- opp-microvolt: CPU voltage triplet. 24c66ec88fSEmmanuel Vadot 25c66ec88fSEmmanuel VadotOptional properties: 26c66ec88fSEmmanuel Vadot- cpu-supply: Phandle to the CPU power supply. 27c66ec88fSEmmanuel Vadot 28c66ec88fSEmmanuel VadotExample: 29c66ec88fSEmmanuel Vadot regulators { 30c66ec88fSEmmanuel Vadot cpu_reg: regulator0 { 31c66ec88fSEmmanuel Vadot regulator-name = "vdd_cpu"; 32c66ec88fSEmmanuel Vadot }; 33c66ec88fSEmmanuel Vadot }; 34c66ec88fSEmmanuel Vadot 35c66ec88fSEmmanuel Vadot cpu0_opp_table: opp_table0 { 36c66ec88fSEmmanuel Vadot compatible = "operating-points-v2"; 37c66ec88fSEmmanuel Vadot 38c66ec88fSEmmanuel Vadot opp@456000000 { 39c66ec88fSEmmanuel Vadot clock-latency-ns = <125000>; 40c66ec88fSEmmanuel Vadot opp-microvolt = <825000 825000 1125000>; 41c66ec88fSEmmanuel Vadot opp-supported-hw = <0x03 0x0001>; 42c66ec88fSEmmanuel Vadot opp-hz = /bits/ 64 <456000000>; 43c66ec88fSEmmanuel Vadot }; 44c66ec88fSEmmanuel Vadot 45c66ec88fSEmmanuel Vadot ... 46c66ec88fSEmmanuel Vadot }; 47c66ec88fSEmmanuel Vadot 48c66ec88fSEmmanuel Vadot cpus { 49c66ec88fSEmmanuel Vadot cpu@0 { 50c66ec88fSEmmanuel Vadot compatible = "arm,cortex-a9"; 51c66ec88fSEmmanuel Vadot clocks = <&tegra_car TEGRA20_CLK_CCLK>; 52c66ec88fSEmmanuel Vadot operating-points-v2 = <&cpu0_opp_table>; 53c66ec88fSEmmanuel Vadot cpu-supply = <&cpu_reg>; 54c66ec88fSEmmanuel Vadot #cooling-cells = <2>; 55c66ec88fSEmmanuel Vadot }; 56c66ec88fSEmmanuel Vadot }; 57