xref: /freebsd/sys/contrib/device-tree/Bindings/cpufreq/cpufreq-qcom-hw.yaml (revision d0b2dbfa0ecf2bbc9709efc5e20baf8e4b44bbbf) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - enum:
24              - qcom,qcm2290-cpufreq-hw
25              - qcom,sc7180-cpufreq-hw
26              - qcom,sdm845-cpufreq-hw
27              - qcom,sm6115-cpufreq-hw
28              - qcom,sm6350-cpufreq-hw
29              - qcom,sm8150-cpufreq-hw
30          - const: qcom,cpufreq-hw
31
32      - description: v2 of CPUFREQ HW (EPSS)
33        items:
34          - enum:
35              - qcom,qdu1000-cpufreq-epss
36              - qcom,sa8775p-cpufreq-epss
37              - qcom,sc7280-cpufreq-epss
38              - qcom,sc8280xp-cpufreq-epss
39              - qcom,sm6375-cpufreq-epss
40              - qcom,sm8250-cpufreq-epss
41              - qcom,sm8350-cpufreq-epss
42              - qcom,sm8450-cpufreq-epss
43              - qcom,sm8550-cpufreq-epss
44          - const: qcom,cpufreq-epss
45
46  reg:
47    minItems: 1
48    items:
49      - description: Frequency domain 0 register region
50      - description: Frequency domain 1 register region
51      - description: Frequency domain 2 register region
52
53  reg-names:
54    minItems: 1
55    items:
56      - const: freq-domain0
57      - const: freq-domain1
58      - const: freq-domain2
59
60  clocks:
61    items:
62      - description: XO Clock
63      - description: GPLL0 Clock
64
65  clock-names:
66    items:
67      - const: xo
68      - const: alternate
69
70  interrupts:
71    minItems: 1
72    maxItems: 3
73
74  interrupt-names:
75    minItems: 1
76    items:
77      - const: dcvsh-irq-0
78      - const: dcvsh-irq-1
79      - const: dcvsh-irq-2
80
81  '#freq-domain-cells':
82    const: 1
83
84  '#clock-cells':
85    const: 1
86
87required:
88  - compatible
89  - reg
90  - clocks
91  - clock-names
92  - '#freq-domain-cells'
93
94additionalProperties: false
95
96allOf:
97  - if:
98      properties:
99        compatible:
100          contains:
101            enum:
102              - qcom,qcm2290-cpufreq-hw
103    then:
104      properties:
105        reg:
106          minItems: 1
107          maxItems: 1
108
109        reg-names:
110          minItems: 1
111          maxItems: 1
112
113        interrupts:
114          minItems: 1
115          maxItems: 1
116
117        interrupt-names:
118          minItems: 1
119
120  - if:
121      properties:
122        compatible:
123          contains:
124            enum:
125              - qcom,qdu1000-cpufreq-epss
126              - qcom,sc7180-cpufreq-hw
127              - qcom,sc8280xp-cpufreq-epss
128              - qcom,sdm845-cpufreq-hw
129              - qcom,sm6115-cpufreq-hw
130              - qcom,sm6350-cpufreq-hw
131              - qcom,sm6375-cpufreq-epss
132    then:
133      properties:
134        reg:
135          minItems: 2
136          maxItems: 2
137
138        reg-names:
139          minItems: 2
140          maxItems: 2
141
142        interrupts:
143          minItems: 2
144          maxItems: 2
145
146        interrupt-names:
147          minItems: 2
148
149  - if:
150      properties:
151        compatible:
152          contains:
153            enum:
154              - qcom,sc7280-cpufreq-epss
155              - qcom,sm8250-cpufreq-epss
156              - qcom,sm8350-cpufreq-epss
157              - qcom,sm8450-cpufreq-epss
158              - qcom,sm8550-cpufreq-epss
159    then:
160      properties:
161        reg:
162          minItems: 3
163          maxItems: 3
164
165        reg-names:
166          minItems: 3
167          maxItems: 3
168
169        interrupts:
170          minItems: 3
171          maxItems: 3
172
173        interrupt-names:
174          minItems: 3
175
176  - if:
177      properties:
178        compatible:
179          contains:
180            enum:
181              - qcom,sm8150-cpufreq-hw
182    then:
183      properties:
184        reg:
185          minItems: 3
186          maxItems: 3
187
188        reg-names:
189          minItems: 3
190          maxItems: 3
191
192        # On some SoCs the Prime core shares the LMH irq with Big cores
193        interrupts:
194          minItems: 2
195          maxItems: 2
196
197        interrupt-names:
198          minItems: 2
199
200
201examples:
202  - |
203    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
204    #include <dt-bindings/clock/qcom,rpmh.h>
205
206    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
207    // switch DCVS state together.
208    cpus {
209      #address-cells = <2>;
210      #size-cells = <0>;
211
212      CPU0: cpu@0 {
213        device_type = "cpu";
214        compatible = "qcom,kryo385";
215        reg = <0x0 0x0>;
216        enable-method = "psci";
217        next-level-cache = <&L2_0>;
218        qcom,freq-domain = <&cpufreq_hw 0>;
219        clocks = <&cpufreq_hw 0>;
220        L2_0: l2-cache {
221          compatible = "cache";
222          cache-unified;
223          cache-level = <2>;
224          next-level-cache = <&L3_0>;
225          L3_0: l3-cache {
226            compatible = "cache";
227            cache-unified;
228            cache-level = <3>;
229          };
230        };
231      };
232
233      CPU1: cpu@100 {
234        device_type = "cpu";
235        compatible = "qcom,kryo385";
236        reg = <0x0 0x100>;
237        enable-method = "psci";
238        next-level-cache = <&L2_100>;
239        qcom,freq-domain = <&cpufreq_hw 0>;
240        clocks = <&cpufreq_hw 0>;
241        L2_100: l2-cache {
242          compatible = "cache";
243          cache-unified;
244          cache-level = <2>;
245          next-level-cache = <&L3_0>;
246        };
247      };
248
249      CPU2: cpu@200 {
250        device_type = "cpu";
251        compatible = "qcom,kryo385";
252        reg = <0x0 0x200>;
253        enable-method = "psci";
254        next-level-cache = <&L2_200>;
255        qcom,freq-domain = <&cpufreq_hw 0>;
256        clocks = <&cpufreq_hw 0>;
257        L2_200: l2-cache {
258          compatible = "cache";
259          cache-unified;
260          cache-level = <2>;
261          next-level-cache = <&L3_0>;
262        };
263      };
264
265      CPU3: cpu@300 {
266        device_type = "cpu";
267        compatible = "qcom,kryo385";
268        reg = <0x0 0x300>;
269        enable-method = "psci";
270        next-level-cache = <&L2_300>;
271        qcom,freq-domain = <&cpufreq_hw 0>;
272        clocks = <&cpufreq_hw 0>;
273        L2_300: l2-cache {
274          compatible = "cache";
275          cache-unified;
276          cache-level = <2>;
277          next-level-cache = <&L3_0>;
278        };
279      };
280
281      CPU4: cpu@400 {
282        device_type = "cpu";
283        compatible = "qcom,kryo385";
284        reg = <0x0 0x400>;
285        enable-method = "psci";
286        next-level-cache = <&L2_400>;
287        qcom,freq-domain = <&cpufreq_hw 1>;
288        clocks = <&cpufreq_hw 1>;
289        L2_400: l2-cache {
290          compatible = "cache";
291          cache-unified;
292          cache-level = <2>;
293          next-level-cache = <&L3_0>;
294        };
295      };
296
297      CPU5: cpu@500 {
298        device_type = "cpu";
299        compatible = "qcom,kryo385";
300        reg = <0x0 0x500>;
301        enable-method = "psci";
302        next-level-cache = <&L2_500>;
303        qcom,freq-domain = <&cpufreq_hw 1>;
304        clocks = <&cpufreq_hw 1>;
305        L2_500: l2-cache {
306          compatible = "cache";
307          cache-unified;
308          cache-level = <2>;
309          next-level-cache = <&L3_0>;
310        };
311      };
312
313      CPU6: cpu@600 {
314        device_type = "cpu";
315        compatible = "qcom,kryo385";
316        reg = <0x0 0x600>;
317        enable-method = "psci";
318        next-level-cache = <&L2_600>;
319        qcom,freq-domain = <&cpufreq_hw 1>;
320        clocks = <&cpufreq_hw 1>;
321        L2_600: l2-cache {
322          compatible = "cache";
323          cache-unified;
324          cache-level = <2>;
325          next-level-cache = <&L3_0>;
326        };
327      };
328
329      CPU7: cpu@700 {
330        device_type = "cpu";
331        compatible = "qcom,kryo385";
332        reg = <0x0 0x700>;
333        enable-method = "psci";
334        next-level-cache = <&L2_700>;
335        qcom,freq-domain = <&cpufreq_hw 1>;
336        clocks = <&cpufreq_hw 1>;
337        L2_700: l2-cache {
338          compatible = "cache";
339          cache-unified;
340          cache-level = <2>;
341          next-level-cache = <&L3_0>;
342        };
343      };
344    };
345
346    soc {
347      #address-cells = <1>;
348      #size-cells = <1>;
349
350      cpufreq@17d43000 {
351        compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
352        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
353        reg-names = "freq-domain0", "freq-domain1";
354
355        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
356        clock-names = "xo", "alternate";
357
358        #freq-domain-cells = <1>;
359        #clock-cells = <1>;
360      };
361    };
362...
363