1Device Tree Clock bindings for the Zynq 7000 EPP 2 3The Zynq EPP has several different clk providers, each with there own bindings. 4The purpose of this document is to document their usage. 5 6See clock_bindings.txt for more information on the generic clock bindings. 7See Chapter 25 of Zynq TRM for more information about Zynq clocks. 8 9== Clock Controller == 10The clock controller is a logical abstraction of Zynq's clock tree. It reads 11required input clock frequencies from the devicetree and acts as clock provider 12for all clock consumers of PS clocks. 13 14Required properties: 15 - #clock-cells : Must be 1 16 - compatible : "xlnx,ps7-clkc" 17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 > 18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ 19 (usually 33 MHz oscillators are used for Zynq platforms) 20 - clock-output-names : List of strings used to name the clock outputs. Shall be 21 a list of the outputs given below. 22 23Optional properties: 24 - clocks : as described in the clock bindings 25 - clock-names : as described in the clock bindings 26 - fclk-enable : Bit mask to enable FCLKs statically at boot time. 27 Bit [0..3] correspond to FCLK0..FCLK3. The corresponding 28 FCLK will only be enabled if it is actually running at 29 boot time. 30 31Clock inputs: 32The following strings are optional parameters to the 'clock-names' property in 33order to provide an optional (E)MIO clock source. 34 - swdt_ext_clk 35 - gem0_emio_clk 36 - gem1_emio_clk 37 - mio_clk_XX # with XX = 00..53 38... 39 40Clock outputs: 41 0: armpll 42 1: ddrpll 43 2: iopll 44 3: cpu_6or4x 45 4: cpu_3or2x 46 5: cpu_2x 47 6: cpu_1x 48 7: ddr2x 49 8: ddr3x 50 9: dci 51 10: lqspi 52 11: smc 53 12: pcap 54 13: gem0 55 14: gem1 56 15: fclk0 57 16: fclk1 58 17: fclk2 59 18: fclk3 60 19: can0 61 20: can1 62 21: sdio0 63 22: sdio1 64 23: uart0 65 24: uart1 66 25: spi0 67 26: spi1 68 27: dma 69 28: usb0_aper 70 29: usb1_aper 71 30: gem0_aper 72 31: gem1_aper 73 32: sdio0_aper 74 33: sdio1_aper 75 34: spi0_aper 76 35: spi1_aper 77 36: can0_aper 78 37: can1_aper 79 38: i2c0_aper 80 39: i2c1_aper 81 40: uart0_aper 82 41: uart1_aper 83 42: gpio_aper 84 43: lqspi_aper 85 44: smc_aper 86 45: swdt 87 46: dbg_trc 88 47: dbg_apb 89 90Example: 91 clkc: clkc@100 { 92 #clock-cells = <1>; 93 compatible = "xlnx,ps7-clkc"; 94 ps-clk-frequency = <33333333>; 95 reg = <0x100 0x100>; 96 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 97 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 98 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 99 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 100 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 101 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 102 "gem1_aper", "sdio0_aper", "sdio1_aper", 103 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 104 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 105 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 106 "dbg_trc", "dbg_apb"; 107 # optional props 108 clocks = <&clkc 16>, <&clk_foo>; 109 clock-names = "gem1_emio_clk", "can_mio_clk_23"; 110 }; 111