1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx Versal clock controller 8 9maintainers: 10 - Michal Simek <michal.simek@xilinx.com> 11 - Jolly Shah <jolly.shah@xilinx.com> 12 - Rajan Vaja <rajan.vaja@xilinx.com> 13 14description: | 15 The clock controller is a hardware block of Xilinx versal clock tree. It 16 reads required input clock frequencies from the devicetree and acts as clock 17 provider for all clock consumers of PS clocks. 18 19select: false 20 21properties: 22 compatible: 23 const: xlnx,versal-clk 24 25 "#clock-cells": 26 const: 1 27 28 clocks: 29 description: List of clock specifiers which are external input 30 clocks to the given clock controller. 31 items: 32 - description: reference clock 33 - description: alternate reference clock 34 - description: alternate reference clock for programmable logic 35 36 clock-names: 37 items: 38 - const: ref 39 - const: alt_ref 40 - const: pl_alt_ref 41 42required: 43 - compatible 44 - "#clock-cells" 45 - clocks 46 - clock-names 47 48additionalProperties: false 49 50examples: 51 - | 52 firmware { 53 zynqmp_firmware: zynqmp-firmware { 54 compatible = "xlnx,zynqmp-firmware"; 55 method = "smc"; 56 versal_clk: clock-controller { 57 #clock-cells = <1>; 58 compatible = "xlnx,versal-clk"; 59 clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>; 60 clock-names = "ref", "alt_ref", "pl_alt_ref"; 61 }; 62 }; 63 }; 64... 65