1Binding for Texas Instruments DPLL clock. 2 3Binding status: Unstable - ABI compatibility may be broken in the future 4 5This binding uses the common clock binding[1]. It assumes a 6register-mapped DPLL with usually two selectable input clocks 7(reference clock and bypass clock), with digital phase locked 8loop logic for multiplying the input clock to a desired output 9clock. This clock also typically supports different operation 10modes (locked, low power stop etc.) This binding has several 11sub-types, which effectively result in slightly different setup 12for the actual DPLL clock. 13 14[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 15 16Required properties: 17- compatible : shall be one of: 18 "ti,omap3-dpll-clock", 19 "ti,omap3-dpll-core-clock", 20 "ti,omap3-dpll-per-clock", 21 "ti,omap3-dpll-per-j-type-clock", 22 "ti,omap4-dpll-clock", 23 "ti,omap4-dpll-x2-clock", 24 "ti,omap4-dpll-core-clock", 25 "ti,omap4-dpll-m4xen-clock", 26 "ti,omap4-dpll-j-type-clock", 27 "ti,omap5-mpu-dpll-clock", 28 "ti,am3-dpll-no-gate-clock", 29 "ti,am3-dpll-j-type-clock", 30 "ti,am3-dpll-no-gate-j-type-clock", 31 "ti,am3-dpll-clock", 32 "ti,am3-dpll-core-clock", 33 "ti,am3-dpll-x2-clock", 34 "ti,omap2-dpll-core-clock", 35 36- #clock-cells : from common clock binding; shall be set to 0. 37- clocks : link phandles of parent clocks, first entry lists reference clock 38 and second entry bypass clock 39- reg : offsets for the register set for controlling the DPLL. 40 Registers are listed in following order: 41 "control" - contains the control register base address 42 "idlest" - contains the idle status register base address 43 "mult-div1" - contains the multiplier / divider register base address 44 "autoidle" - contains the autoidle register base address (optional) 45 ti,am3-* dpll types do not have autoidle register 46 ti,omap2-* dpll type does not support idlest / autoidle registers 47 48Optional properties: 49- DPLL mode setting - defining any one or more of the following overrides 50 default setting. 51 - ti,low-power-stop : DPLL supports low power stop mode, gating output 52 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock 53 - ti,lock : DPLL locks in programmed rate 54 55Examples: 56 dpll_core_ck: dpll_core_ck@44e00490 { 57 #clock-cells = <0>; 58 compatible = "ti,omap4-dpll-core-clock"; 59 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 60 reg = <0x490>, <0x45c>, <0x488>, <0x468>; 61 }; 62 63 dpll2_ck: dpll2_ck@48004004 { 64 #clock-cells = <0>; 65 compatible = "ti,omap3-dpll-clock"; 66 clocks = <&sys_ck>, <&dpll2_fck>; 67 ti,low-power-stop; 68 ti,low-power-bypass; 69 ti,lock; 70 reg = <0x4>, <0x24>, <0x34>, <0x40>; 71 }; 72 73 dpll_core_ck: dpll_core_ck@44e00490 { 74 #clock-cells = <0>; 75 compatible = "ti,am3-dpll-core-clock"; 76 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 77 reg = <0x90>, <0x5c>, <0x68>; 78 }; 79 80 dpll_ck: dpll_ck { 81 #clock-cells = <0>; 82 compatible = "ti,omap2-dpll-core-clock"; 83 clocks = <&sys_ck>, <&sys_ck>; 84 reg = <0x0500>, <0x0540>; 85 }; 86