1Binding for TI divider clock 2 3This binding uses the common clock binding[1]. It assumes a 4register-mapped adjustable clock rate divider that does not gate and has 5only one input clock or parent. By default the value programmed into 6the register is one less than the actual divisor value. E.g: 7 8register value actual divisor value 90 1 101 2 112 3 12 13This assumption may be modified by the following optional properties: 14 15ti,index-starts-at-one - valid divisor values start at 1, not the default 16of 0. E.g: 17register value actual divisor value 181 1 192 2 203 3 21 22ti,index-power-of-two - valid divisor values are powers of two. E.g: 23register value actual divisor value 240 1 251 2 262 4 27 28Additionally an array of valid dividers may be supplied like so: 29 30 ti,dividers = <4>, <8>, <0>, <16>; 31 32Which will map the resulting values to a divisor table by their index: 33register value actual divisor value 340 4 351 8 362 <invalid divisor, skipped> 373 16 38 39Any zero value in this array means the corresponding bit-value is invalid 40and must not be used. 41 42The binding must also provide the register to control the divider and 43unless the divider array is provided, min and max dividers. Optionally 44the number of bits to shift that mask, if necessary. If the shift value 45is missing it is the same as supplying a zero shift. 46 47This binding can also optionally provide support to the hardware autoidle 48feature, see [2]. 49 50[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 51[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt 52 53Required properties: 54- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock". 55- #clock-cells : from common clock binding; shall be set to 0. 56- clocks : link to phandle of parent clock 57- reg : offset for register controlling adjustable divider 58 59Optional properties: 60- clock-output-names : from common clock binding. 61- ti,dividers : array of integers defining divisors 62- ti,bit-shift : number of bits to shift the divider value, defaults to 0 63- ti,min-div : min divisor for dividing the input clock rate, only 64 needed if the first divisor is offset from the default value (1) 65- ti,max-div : max divisor for dividing the input clock rate, only needed 66 if ti,dividers is not defined. 67- ti,index-starts-at-one : valid divisor programming starts at 1, not zero, 68 only valid if ti,dividers is not defined. 69- ti,index-power-of-two : valid divisor programming must be a power of two, 70 only valid if ti,dividers is not defined. 71- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock, 72 see [2] 73- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0, 74 see [2] 75- ti,set-rate-parent : clk_set_rate is propagated to parent 76- ti,latch-bit : latch the divider value to HW, only needed if the register 77 access requires this. As an example dra76x DPLL_GMAC H14 divider implements 78 such behavior. 79 80Examples: 81dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { 82 #clock-cells = <0>; 83 compatible = "ti,divider-clock"; 84 clocks = <&dpll_usb_ck>; 85 ti,max-div = <127>; 86 reg = <0x190>; 87 ti,index-starts-at-one; 88}; 89 90aess_fclk: aess_fclk@4a004528 { 91 #clock-cells = <0>; 92 compatible = "ti,divider-clock"; 93 clocks = <&abe_clk>; 94 ti,bit-shift = <24>; 95 reg = <0x528>; 96 ti,max-div = <2>; 97}; 98 99dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck { 100 #clock-cells = <0>; 101 compatible = "ti,composite-divider-clock"; 102 clocks = <&dpll_core_x2_ck>; 103 ti,max-div = <31>; 104 reg = <0x0134>; 105 ti,index-starts-at-one; 106}; 107 108ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 { 109 #clock-cells = <0>; 110 compatible = "ti,composite-divider-clock"; 111 clocks = <&corex2_fck>; 112 ti,bit-shift = <8>; 113 reg = <0x0a40>; 114 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; 115}; 116