1*aa1a8ff2SEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 28bab661aSEmmanuel Vadot%YAML 1.2 38bab661aSEmmanuel Vadot--- 48bab661aSEmmanuel Vadot$id: http://devicetree.org/schemas/clock/ti,cdce925.yaml# 58bab661aSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 68bab661aSEmmanuel Vadot 78bab661aSEmmanuel Vadottitle: TI CDCE913/925/937/949 programmable I2C clock synthesizers 88bab661aSEmmanuel Vadot 98bab661aSEmmanuel Vadotmaintainers: 108bab661aSEmmanuel Vadot - Alexander Stein <alexander.stein@ew.tq-group.com> 118bab661aSEmmanuel Vadot 128bab661aSEmmanuel Vadotdescription: | 138bab661aSEmmanuel Vadot Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction 148bab661aSEmmanuel Vadot 158bab661aSEmmanuel Vadot - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913 168bab661aSEmmanuel Vadot - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925 178bab661aSEmmanuel Vadot - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937 188bab661aSEmmanuel Vadot - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949 198bab661aSEmmanuel Vadot 208bab661aSEmmanuel Vadotproperties: 218bab661aSEmmanuel Vadot compatible: 228bab661aSEmmanuel Vadot enum: 238bab661aSEmmanuel Vadot - ti,cdce913 248bab661aSEmmanuel Vadot - ti,cdce925 258bab661aSEmmanuel Vadot - ti,cdce937 268bab661aSEmmanuel Vadot - ti,cdce949 278bab661aSEmmanuel Vadot 288bab661aSEmmanuel Vadot reg: 298bab661aSEmmanuel Vadot maxItems: 1 308bab661aSEmmanuel Vadot 318bab661aSEmmanuel Vadot clocks: 328bab661aSEmmanuel Vadot items: 338bab661aSEmmanuel Vadot - description: fixed parent clock 348bab661aSEmmanuel Vadot 358bab661aSEmmanuel Vadot "#clock-cells": 368bab661aSEmmanuel Vadot const: 1 378bab661aSEmmanuel Vadot 388bab661aSEmmanuel Vadot vdd-supply: 398bab661aSEmmanuel Vadot description: Regulator that provides 1.8V Vdd power supply 408bab661aSEmmanuel Vadot 418bab661aSEmmanuel Vadot vddout-supply: 428bab661aSEmmanuel Vadot description: | 438bab661aSEmmanuel Vadot Regulator that provides Vddout power supply. 448bab661aSEmmanuel Vadot non-L variant: 2.5V or 3.3V for 458bab661aSEmmanuel Vadot L variant: 1.8V for 468bab661aSEmmanuel Vadot 478bab661aSEmmanuel Vadot xtal-load-pf: 488bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 498bab661aSEmmanuel Vadot description: | 508bab661aSEmmanuel Vadot Crystal load-capacitor value to fine-tune performance on a 518bab661aSEmmanuel Vadot board, or to compensate for external influences. 528bab661aSEmmanuel Vadot 538bab661aSEmmanuel VadotpatternProperties: 548bab661aSEmmanuel Vadot "^PLL[1-4]$": 558bab661aSEmmanuel Vadot type: object 568bab661aSEmmanuel Vadot description: | 578bab661aSEmmanuel Vadot optional child node can be used to specify spread 588bab661aSEmmanuel Vadot spectrum clocking parameters for a board 598bab661aSEmmanuel Vadot 608bab661aSEmmanuel Vadot additionalProperties: false 618bab661aSEmmanuel Vadot 628bab661aSEmmanuel Vadot properties: 638bab661aSEmmanuel Vadot spread-spectrum: 648bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 658bab661aSEmmanuel Vadot description: SSC mode as defined in the data sheet 668bab661aSEmmanuel Vadot 678bab661aSEmmanuel Vadot spread-spectrum-center: 688bab661aSEmmanuel Vadot type: boolean 698bab661aSEmmanuel Vadot description: | 708bab661aSEmmanuel Vadot Use "centered" mode instead of "max" mode. When 718bab661aSEmmanuel Vadot present, the clock runs at the requested frequency on average. 728bab661aSEmmanuel Vadot Otherwise the requested frequency is the maximum value of the 738bab661aSEmmanuel Vadot SCC range. 748bab661aSEmmanuel Vadot 758bab661aSEmmanuel Vadotrequired: 768bab661aSEmmanuel Vadot - compatible 778bab661aSEmmanuel Vadot - reg 788bab661aSEmmanuel Vadot - clocks 798bab661aSEmmanuel Vadot - "#clock-cells" 808bab661aSEmmanuel Vadot 818bab661aSEmmanuel VadotadditionalProperties: false 828bab661aSEmmanuel Vadot 838bab661aSEmmanuel Vadotexamples: 848bab661aSEmmanuel Vadot - | 858bab661aSEmmanuel Vadot i2c { 868bab661aSEmmanuel Vadot #address-cells = <1>; 878bab661aSEmmanuel Vadot #size-cells = <0>; 888bab661aSEmmanuel Vadot 898bab661aSEmmanuel Vadot cdce925: clock-controller@64 { 908bab661aSEmmanuel Vadot compatible = "ti,cdce925"; 918bab661aSEmmanuel Vadot reg = <0x64>; 928bab661aSEmmanuel Vadot clocks = <&xtal_27Mhz>; 938bab661aSEmmanuel Vadot #clock-cells = <1>; 948bab661aSEmmanuel Vadot xtal-load-pf = <5>; 958bab661aSEmmanuel Vadot vdd-supply = <®_1v8>; 968bab661aSEmmanuel Vadot vddout-supply = <®_3v3>; 978bab661aSEmmanuel Vadot /* PLL options to get SSC 1% centered */ 988bab661aSEmmanuel Vadot PLL2 { 998bab661aSEmmanuel Vadot spread-spectrum = <4>; 1008bab661aSEmmanuel Vadot spread-spectrum-center; 1018bab661aSEmmanuel Vadot }; 1028bab661aSEmmanuel Vadot }; 1038bab661aSEmmanuel Vadot }; 104