1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: T-HEAD TH1520 AP sub-system clock controller 8 9description: | 10 The T-HEAD TH1520 AP sub-system clock controller configures the 11 CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures 12 the clock gates for the HDMI, MIPI and the GPU. 13 14 SoC reference manual 15 https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf 16 17maintainers: 18 - Jisheng Zhang <jszhang@kernel.org> 19 - Wei Fu <wefu@redhat.com> 20 - Drew Fustini <dfustini@tenstorrent.com> 21 22properties: 23 compatible: 24 enum: 25 - thead,th1520-clk-ap 26 - thead,th1520-clk-vo 27 28 reg: 29 maxItems: 1 30 31 clocks: 32 items: 33 - description: | 34 One input clock: 35 - For "thead,th1520-clk-ap": the clock input must be the 24 MHz 36 main oscillator. 37 - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, 38 which is configured by the AP clock controller. According to the 39 TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL 40 (integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with 41 a maximum FOUTVCO of 2376 MHz. 42 43 "#clock-cells": 44 const: 1 45 description: 46 See <dt-bindings/clock/thead,th1520-clk-ap.h> for valid indices. 47 48required: 49 - compatible 50 - reg 51 - clocks 52 - "#clock-cells" 53 54additionalProperties: false 55 56examples: 57 - | 58 #include <dt-bindings/clock/thead,th1520-clk-ap.h> 59 clock-controller@ef010000 { 60 compatible = "thead,th1520-clk-ap"; 61 reg = <0xef010000 0x1000>; 62 clocks = <&osc>; 63 #clock-cells = <1>; 64 }; 65