1*c66ec88fSEmmanuel Vadot* Sigma Designs Tango4 Clock Generator 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThe Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used 4*c66ec88fSEmmanuel Vadotfor RAM and various peripheral devices). The clock binding described here 5*c66ec88fSEmmanuel Vadotis applicable to all Tango4 SoCs. 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotRequired Properties: 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot- compatible: should be "sigma,tango4-clkgen". 10*c66ec88fSEmmanuel Vadot- reg: physical base address of the device and length of memory mapped region. 11*c66ec88fSEmmanuel Vadot- clocks: phandle of the input clock (crystal oscillator). 12*c66ec88fSEmmanuel Vadot- clock-output-names: should be "cpuclk" and "sysclk". 13*c66ec88fSEmmanuel Vadot- #clock-cells: should be set to 1. 14*c66ec88fSEmmanuel Vadot 15*c66ec88fSEmmanuel VadotExample: 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel Vadot clkgen: clkgen@10000 { 18*c66ec88fSEmmanuel Vadot compatible = "sigma,tango4-clkgen"; 19*c66ec88fSEmmanuel Vadot reg = <0x10000 0x40>; 20*c66ec88fSEmmanuel Vadot clocks = <&xtal>; 21*c66ec88fSEmmanuel Vadot clock-output-names = "cpuclk", "sysclk"; 22*c66ec88fSEmmanuel Vadot #clock-cells = <1>; 23*c66ec88fSEmmanuel Vadot }; 24