xref: /freebsd/sys/contrib/device-tree/Bindings/clock/stericsson,u8500-clks.yaml (revision f374ba41f55c1a127303d92d830dd58eef2f5243) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ST-Ericsson DB8500 (U8500) clocks
8
9maintainers:
10  - Ulf Hansson <ulf.hansson@linaro.org>
11  - Linus Walleij <linus.walleij@linaro.org>
12
13description: While named "U8500 clocks" these clocks are inside the
14  DB8500 digital baseband system-on-chip and its siblings such as
15  DB8520. These bindings consider the clocks present in the SoC
16  itself, not off-chip clocks. There are four different on-chip
17  clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
18  control management unit) clocks and PRCC (peripheral reset and
19  clock controller) clocks. For some reason PRCC 4 does not exist so
20  the itemization can be a bit unintuitive.
21
22properties:
23  compatible:
24    enum:
25      - stericsson,u8500-clks
26      - stericsson,u8540-clks
27      - stericsson,u9540-clks
28
29  reg:
30    items:
31      - description: PRCC 1 register area
32      - description: PRCC 2 register area
33      - description: PRCC 3 register area
34      - description: PRCC 5 register area
35      - description: PRCC 6 register area
36
37  prcmu-clock:
38    description: A subnode with one clock cell for PRCMU (power, reset, control
39      management unit) clocks. The cell indicates which PRCMU clock in the
40      prcmu-clock node the consumer wants to use.
41    type: object
42
43    properties:
44      '#clock-cells':
45        const: 1
46
47    additionalProperties: false
48
49  prcc-periph-clock:
50    description: A subnode with two clock cells for PRCC (peripheral
51      reset and clock controller) peripheral clocks. The first cell indicates
52      which PRCC block the consumer wants to use, possible values are 1, 2, 3,
53      5, 6. The second cell indicates which clock inside the PRCC block it
54      wants, possible values are 0 thru 31.
55    type: object
56
57    properties:
58      '#clock-cells':
59        const: 2
60
61    additionalProperties: false
62
63  prcc-kernel-clock:
64    description: A subnode with two clock cells for PRCC (peripheral reset
65      and clock controller) kernel clocks. The first cell indicates which PRCC
66      block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The
67      second cell indicates which clock inside the PRCC block it wants, possible
68      values are 0 thru 31.
69    type: object
70
71    properties:
72      '#clock-cells':
73        const: 2
74
75    additionalProperties: false
76
77  prcc-reset-controller:
78    description: A subnode with two reset cells for the reset portions of the
79      PRCC (peripheral reset and clock controller). The first cell indicates
80      which PRCC block the consumer wants to use, possible values are 1, 2, 3
81      5 and 6. The second cell indicates which reset line inside the PRCC block
82      it wants to control, possible values are 0 thru 31.
83    type: object
84
85    properties:
86      '#reset-cells':
87        const: 2
88
89    additionalProperties: false
90
91  rtc32k-clock:
92    description: A subnode with zero clock cells for the 32kHz RTC clock.
93    type: object
94
95    properties:
96      '#clock-cells':
97        const: 0
98
99    additionalProperties: false
100
101  smp-twd-clock:
102    description: A subnode for the ARM SMP Timer Watchdog cluster with zero
103      clock cells.
104    type: object
105
106    properties:
107      '#clock-cells':
108        const: 0
109
110    additionalProperties: false
111
112  clkout-clock:
113    description: A subnode with three clock cells for externally routed clocks,
114      output clocks. These are two PRCMU-internal clocks that can be divided and
115      muxed out on the pads of the DB8500 SoC.
116    type: object
117
118    properties:
119      '#clock-cells':
120        description:
121          The first cell indicates which output clock we are using,
122          possible values are 0 (CLKOUT1) and 1 (CLKOUT2).
123          The second cell indicates which clock we want to use as source,
124          possible values are 0 thru 7, see the defines for the different
125          source clocks.
126          The third cell is a divider, legal values are 1 thru 63.
127        const: 3
128
129    additionalProperties: false
130
131required:
132  - compatible
133  - reg
134  - prcmu-clock
135  - prcc-periph-clock
136  - prcc-kernel-clock
137  - rtc32k-clock
138  - smp-twd-clock
139
140additionalProperties: false
141
142examples:
143  - |
144    #include <dt-bindings/clock/ste-db8500-clkout.h>
145    clocks@8012 {
146      compatible = "stericsson,u8500-clks";
147      reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
148            <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
149            <0xa03cf000 0x1000>;
150
151      prcmu_clk: prcmu-clock {
152        #clock-cells = <1>;
153      };
154
155      prcc_pclk: prcc-periph-clock {
156        #clock-cells = <2>;
157      };
158
159      prcc_kclk: prcc-kernel-clock {
160        #clock-cells = <2>;
161      };
162
163      prcc_reset: prcc-reset-controller {
164        #reset-cells = <2>;
165      };
166
167      rtc_clk: rtc32k-clock {
168        #clock-cells = <0>;
169      };
170
171      smp_twd_clk: smp-twd-clock {
172        #clock-cells = <0>;
173      };
174
175      clkout_clk: clkout-clock {
176        #clock-cells = <3>;
177      };
178    };
179