xref: /freebsd/sys/contrib/device-tree/Bindings/clock/st,stm32h7-rcc.txt (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1*c66ec88fSEmmanuel VadotSTMicroelectronics STM32H7 Reset and Clock Controller
2*c66ec88fSEmmanuel Vadot=====================================================
3*c66ec88fSEmmanuel Vadot
4*c66ec88fSEmmanuel VadotThe RCC IP is both a reset and a clock controller.
5*c66ec88fSEmmanuel Vadot
6*c66ec88fSEmmanuel VadotPlease refer to clock-bindings.txt for common clock controller binding usage.
7*c66ec88fSEmmanuel VadotPlease also refer to reset.txt for common reset controller binding usage.
8*c66ec88fSEmmanuel Vadot
9*c66ec88fSEmmanuel VadotRequired properties:
10*c66ec88fSEmmanuel Vadot- compatible: Should be:
11*c66ec88fSEmmanuel Vadot  "st,stm32h743-rcc"
12*c66ec88fSEmmanuel Vadot
13*c66ec88fSEmmanuel Vadot- reg: should be register base and length as documented in the
14*c66ec88fSEmmanuel Vadot  datasheet
15*c66ec88fSEmmanuel Vadot
16*c66ec88fSEmmanuel Vadot- #reset-cells: 1, see below
17*c66ec88fSEmmanuel Vadot
18*c66ec88fSEmmanuel Vadot- #clock-cells : from common clock binding; shall be set to 1
19*c66ec88fSEmmanuel Vadot
20*c66ec88fSEmmanuel Vadot- clocks: External oscillator clock phandle
21*c66ec88fSEmmanuel Vadot  - high speed external clock signal (HSE)
22*c66ec88fSEmmanuel Vadot  - low speed external clock signal (LSE)
23*c66ec88fSEmmanuel Vadot  - external I2S clock (I2S_CKIN)
24*c66ec88fSEmmanuel Vadot
25*c66ec88fSEmmanuel VadotOptional properties:
26*c66ec88fSEmmanuel Vadot- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
27*c66ec88fSEmmanuel Vadot  write protection (RTC clock).
28*c66ec88fSEmmanuel Vadot
29*c66ec88fSEmmanuel VadotExample:
30*c66ec88fSEmmanuel Vadot
31*c66ec88fSEmmanuel Vadot	rcc: reset-clock-controller@58024400 {
32*c66ec88fSEmmanuel Vadot		compatible = "st,stm32h743-rcc", "st,stm32-rcc";
33*c66ec88fSEmmanuel Vadot		reg = <0x58024400 0x400>;
34*c66ec88fSEmmanuel Vadot		#reset-cells = <1>;
35*c66ec88fSEmmanuel Vadot		#clock-cells = <1>;
36*c66ec88fSEmmanuel Vadot		clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
37*c66ec88fSEmmanuel Vadot
38*c66ec88fSEmmanuel Vadot		st,syscfg = <&pwrcfg>;
39*c66ec88fSEmmanuel Vadot};
40*c66ec88fSEmmanuel Vadot
41*c66ec88fSEmmanuel VadotThe peripheral clock consumer should specify the desired clock by
42*c66ec88fSEmmanuel Vadothaving the clock ID in its "clocks" phandle cell.
43*c66ec88fSEmmanuel Vadot
44*c66ec88fSEmmanuel VadotExample:
45*c66ec88fSEmmanuel Vadot
46*c66ec88fSEmmanuel Vadot		timer5: timer@40000c00 {
47*c66ec88fSEmmanuel Vadot			compatible = "st,stm32-timer";
48*c66ec88fSEmmanuel Vadot			reg = <0x40000c00 0x400>;
49*c66ec88fSEmmanuel Vadot			interrupts = <50>;
50*c66ec88fSEmmanuel Vadot			clocks = <&rcc TIM5_CK>;
51*c66ec88fSEmmanuel Vadot		};
52*c66ec88fSEmmanuel Vadot
53*c66ec88fSEmmanuel VadotSpecifying softreset control of devices
54*c66ec88fSEmmanuel Vadot=======================================
55*c66ec88fSEmmanuel Vadot
56*c66ec88fSEmmanuel VadotDevice nodes should specify the reset channel required in their "resets"
57*c66ec88fSEmmanuel Vadotproperty, containing a phandle to the reset device node and an index specifying
58*c66ec88fSEmmanuel Vadotwhich channel to use.
59*c66ec88fSEmmanuel VadotThe index is the bit number within the RCC registers bank, starting from RCC
60*c66ec88fSEmmanuel Vadotbase address.
61*c66ec88fSEmmanuel VadotIt is calculated as: index = register_offset / 4 * 32 + bit_offset.
62*c66ec88fSEmmanuel VadotWhere bit_offset is the bit offset within the register.
63*c66ec88fSEmmanuel Vadot
64*c66ec88fSEmmanuel VadotFor example, for CRC reset:
65*c66ec88fSEmmanuel Vadot  crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
66*c66ec88fSEmmanuel Vadot
67*c66ec88fSEmmanuel VadotExample:
68*c66ec88fSEmmanuel Vadot
69*c66ec88fSEmmanuel Vadot	timer2 {
70*c66ec88fSEmmanuel Vadot		resets	= <&rcc STM32H7_APB1L_RESET(TIM2)>;
71*c66ec88fSEmmanuel Vadot	};
72