1Spreadtrum SC9860 Clock Binding 2------------------------ 3 4Required properties: 5- compatible: should contain the following compatible strings: 6 - "sprd,sc9860-pmu-gate" 7 - "sprd,sc9860-pll" 8 - "sprd,sc9860-ap-clk" 9 - "sprd,sc9860-aon-prediv" 10 - "sprd,sc9860-apahb-gate" 11 - "sprd,sc9860-aon-gate" 12 - "sprd,sc9860-aonsecure-clk" 13 - "sprd,sc9860-agcp-gate" 14 - "sprd,sc9860-gpu-clk" 15 - "sprd,sc9860-vsp-clk" 16 - "sprd,sc9860-vsp-gate" 17 - "sprd,sc9860-cam-clk" 18 - "sprd,sc9860-cam-gate" 19 - "sprd,sc9860-disp-clk" 20 - "sprd,sc9860-disp-gate" 21 - "sprd,sc9860-apapb-gate" 22 23- #clock-cells: must be 1 24 25- clocks : Should be the input parent clock(s) phandle for the clock, this 26 property here just simply shows which clock group the clocks' 27 parents are in, since each clk node would represent many clocks 28 which are defined in the driver. The detailed dependency 29 relationship (i.e. how many parents and which are the parents) 30 are implemented in driver code. 31 32Optional properties: 33 34- reg: Contain the registers base address and length. It must be configured 35 only if no 'sprd,syscon' under the node. 36 37- sprd,syscon: phandle to the syscon which is in the same address area with 38 the clock, and so we can get regmap for the clocks from the 39 syscon device. 40 41Example: 42 43 pmu_gate: pmu-gate { 44 compatible = "sprd,sc9860-pmu-gate"; 45 sprd,syscon = <&pmu_regs>; 46 clocks = <&ext_26m>; 47 #clock-cells = <1>; 48 }; 49 50 pll: pll { 51 compatible = "sprd,sc9860-pll"; 52 sprd,syscon = <&ana_regs>; 53 clocks = <&pmu_gate 0>; 54 #clock-cells = <1>; 55 }; 56 57 ap_clk: clock-controller@20000000 { 58 compatible = "sprd,sc9860-ap-clk"; 59 reg = <0 0x20000000 0 0x400>; 60 clocks = <&ext_26m>, <&pll 0>, 61 <&pmu_gate 0>; 62 #clock-cells = <1>; 63 }; 64