1*c66ec88fSEmmanuel VadotBinding for the AXS10X Generic PLL clock 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThis binding uses the common clock binding[1]. 4*c66ec88fSEmmanuel Vadot 5*c66ec88fSEmmanuel Vadot[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotRequired properties: 8*c66ec88fSEmmanuel Vadot- compatible: should be "snps,axs10x-<name>-pll-clock" 9*c66ec88fSEmmanuel Vadot "snps,axs10x-arc-pll-clock" 10*c66ec88fSEmmanuel Vadot "snps,axs10x-pgu-pll-clock" 11*c66ec88fSEmmanuel Vadot- reg: should always contain 2 pairs address - length: first for PLL config 12*c66ec88fSEmmanuel Vadotregisters and second for corresponding LOCK CGU register. 13*c66ec88fSEmmanuel Vadot- clocks: shall be the input parent clock phandle for the PLL. 14*c66ec88fSEmmanuel Vadot- #clock-cells: from common clock binding; Should always be set to 0. 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel VadotExample: 17*c66ec88fSEmmanuel Vadot input-clk: input-clk { 18*c66ec88fSEmmanuel Vadot clock-frequency = <33333333>; 19*c66ec88fSEmmanuel Vadot compatible = "fixed-clock"; 20*c66ec88fSEmmanuel Vadot #clock-cells = <0>; 21*c66ec88fSEmmanuel Vadot }; 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel Vadot core-clk: core-clk@80 { 24*c66ec88fSEmmanuel Vadot compatible = "snps,axs10x-arc-pll-clock"; 25*c66ec88fSEmmanuel Vadot reg = <0x80 0x10>, <0x100 0x10>; 26*c66ec88fSEmmanuel Vadot #clock-cells = <0>; 27*c66ec88fSEmmanuel Vadot clocks = <&input-clk>; 28*c66ec88fSEmmanuel Vadot }; 29