1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2020 SiFive, Inc. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) 9 10maintainers: 11 - Sagar Kadam <sagar.kadam@sifive.com> 12 - Paul Walmsley <paul.walmsley@sifive.com> 13 14description: 15 On the FU540 family of SoCs, most system-wide clock and reset integration 16 is via the PRCI IP block. 17 The clock consumer should specify the desired clock via the clock ID 18 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. 19 These macros begin with PRCI_CLK_. 20 21 The hfclk and rtcclk nodes are required, and represent physical 22 crystals or resonators located on the PCB. These nodes should be present 23 underneath /, rather than /soc. 24 25properties: 26 compatible: 27 const: sifive,fu540-c000-prci 28 29 reg: 30 maxItems: 1 31 32 clocks: 33 items: 34 - description: high frequency clock. 35 - description: RTL clock. 36 37 clock-names: 38 items: 39 - const: hfclk 40 - const: rtcclk 41 42 "#clock-cells": 43 const: 1 44 45required: 46 - compatible 47 - reg 48 - clocks 49 - "#clock-cells" 50 51additionalProperties: false 52 53examples: 54 - | 55 prci: clock-controller@10000000 { 56 compatible = "sifive,fu540-c000-prci"; 57 reg = <0x10000000 0x1000>; 58 clocks = <&hfclk>, <&rtcclk>; 59 #clock-cells = <1>; 60 }; 61