xref: /freebsd/sys/contrib/device-tree/Bindings/clock/samsung,exynos-audss-clock.yaml (revision 2e3507c25e42292b45a5482e116d278f5515d04d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC Audio SubSystem clock controller
8
9maintainers:
10  - Chanwoo Choi <cw00.choi@samsung.com>
11  - Krzysztof Kozlowski <krzk@kernel.org>
12  - Sylwester Nawrocki <s.nawrocki@samsung.com>
13  - Tomasz Figa <tomasz.figa@gmail.com>
14
15description: |
16  All available clocks are defined as preprocessor macros in
17  include/dt-bindings/clock/exynos-audss-clk.h header.
18
19properties:
20  compatible:
21    enum:
22      - samsung,exynos4210-audss-clock
23      - samsung,exynos5250-audss-clock
24      - samsung,exynos5410-audss-clock
25      - samsung,exynos5420-audss-clock
26
27  clocks:
28    minItems: 2
29    items:
30      - description:
31          Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
32          used if not specified.
33      - description:
34          Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
35          used if not specified.
36      - description:
37          Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
38          specified.
39      - description:
40          PCM clock, parent of sclk_pcm.  "sclk_pcm0" is used if not specified.
41      - description:
42          External i2s clock, parent of mout_i2s. "cdclk0" is used if not
43          specified.
44
45  clock-names:
46    minItems: 2
47    items:
48      - const: pll_ref
49      - const: pll_in
50      - const: sclk_audio
51      - const: sclk_pcm_in
52      - const: cdclk
53
54  "#clock-cells":
55    const: 1
56
57  power-domains:
58    maxItems: 1
59
60  reg:
61    maxItems: 1
62
63required:
64  - compatible
65  - clocks
66  - clock-names
67  - "#clock-cells"
68  - reg
69
70additionalProperties: false
71
72examples:
73  - |
74    clock-controller@3810000 {
75        compatible = "samsung,exynos5250-audss-clock";
76        reg = <0x03810000 0x0c>;
77        #clock-cells = <1>;
78        clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
79        clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
80    };
81