1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip rk3588 Family Clock and Reset Control Module 8 9maintainers: 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 12 13description: | 14 The RK3588 clock controller generates the clock and also implements a reset 15 controller for SoC peripherals. For example it provides SCLK_UART2 and 16 PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART 17 module. 18 Each clock is assigned an identifier and client nodes can use this identifier 19 to specify the clock which they consume. All available clock and reset IDs 20 are defined as preprocessor macros in dt-binding headers. 21 22properties: 23 compatible: 24 enum: 25 - rockchip,rk3588-cru 26 27 reg: 28 maxItems: 1 29 30 "#clock-cells": 31 const: 1 32 33 "#reset-cells": 34 const: 1 35 36 clocks: 37 minItems: 2 38 maxItems: 2 39 40 clock-names: 41 items: 42 - const: xin24m 43 - const: xin32k 44 45 assigned-clocks: true 46 47 assigned-clock-rates: true 48 49 rockchip,grf: 50 $ref: /schemas/types.yaml#/definitions/phandle 51 description: > 52 phandle to the syscon managing the "general register files". It is used 53 for GRF muxes, if missing any muxes present in the GRF will not be 54 available. 55 56required: 57 - compatible 58 - reg 59 - "#clock-cells" 60 - "#reset-cells" 61 62additionalProperties: false 63 64examples: 65 - | 66 cru: clock-controller@fd7c0000 { 67 compatible = "rockchip,rk3588-cru"; 68 reg = <0xfd7c0000 0x5c000>; 69 #clock-cells = <1>; 70 #reset-cells = <1>; 71 }; 72