1* Rockchip RK3399 Clock and Reset Unit 2 3The RK3399 clock controller generates and supplies clock to various 4controllers within the SoC and also implements a reset controller for SoC 5peripherals. 6 7Required Properties: 8 9- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" 10- compatible: CRU should be "rockchip,rk3399-cru" 11- reg: physical base address of the controller and length of memory mapped 12 region. 13- #clock-cells: should be 1. 14- #reset-cells: should be 1. 15 16Optional Properties: 17 18- rockchip,grf: phandle to the syscon managing the "general register files". 19 It is used for GRF muxes, if missing any muxes present in the GRF will not 20 be available. 21 22Each clock is assigned an identifier and client nodes can use this identifier 23to specify the clock which they consume. All available clocks are defined as 24preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be 25used in device tree sources. Similar macros exist for the reset sources in 26these files. 27 28External clocks: 29 30There are several clocks that are generated outside the SoC. It is expected 31that they are defined using standard clock bindings with following 32clock-output-names: 33 - "xin24m" - crystal input - required, 34 - "xin32k" - rtc clock - optional, 35 - "clkin_gmac" - external GMAC clock - optional, 36 - "clkin_i2s" - external I2S clock - optional, 37 - "pclkin_cif" - external ISP clock - optional, 38 - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 39 - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 40 41Example: Clock controller node: 42 43 pmucru: pmu-clock-controller@ff750000 { 44 compatible = "rockchip,rk3399-pmucru"; 45 reg = <0x0 0xff750000 0x0 0x1000>; 46 #clock-cells = <1>; 47 #reset-cells = <1>; 48 }; 49 50 cru: clock-controller@ff760000 { 51 compatible = "rockchip,rk3399-cru"; 52 reg = <0x0 0xff760000 0x0 0x1000>; 53 #clock-cells = <1>; 54 #reset-cells = <1>; 55 }; 56 57Example: UART controller node that consumes the clock generated by the clock 58 controller: 59 60 uart0: serial@ff1a0000 { 61 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 62 reg = <0x0 0xff180000 0x0 0x100>; 63 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 64 clock-names = "baudclk", "apb_pclk"; 65 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 66 reg-shift = <2>; 67 reg-io-width = <4>; 68 }; 69