1*5f62a964SEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0 2*5f62a964SEmmanuel Vadot%YAML 1.2 3*5f62a964SEmmanuel Vadot--- 4*5f62a964SEmmanuel Vadot$id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml# 5*5f62a964SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5f62a964SEmmanuel Vadot 7*5f62a964SEmmanuel Vadottitle: Rockchip RK3328 Clock and Reset Unit (CRU) 8*5f62a964SEmmanuel Vadot 9*5f62a964SEmmanuel Vadotmaintainers: 10*5f62a964SEmmanuel Vadot - Elaine Zhang <zhangqing@rock-chips.com> 11*5f62a964SEmmanuel Vadot - Heiko Stuebner <heiko@sntech.de> 12*5f62a964SEmmanuel Vadot 13*5f62a964SEmmanuel Vadotdescription: | 14*5f62a964SEmmanuel Vadot The RK3328 clock controller generates and supplies clocks to various 15*5f62a964SEmmanuel Vadot controllers within the SoC and also implements a reset controller for SoC 16*5f62a964SEmmanuel Vadot peripherals. 17*5f62a964SEmmanuel Vadot Each clock is assigned an identifier and client nodes can use this identifier 18*5f62a964SEmmanuel Vadot to specify the clock which they consume. All available clocks are defined as 19*5f62a964SEmmanuel Vadot preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be 20*5f62a964SEmmanuel Vadot used in device tree sources. Similar macros exist for the reset sources in 21*5f62a964SEmmanuel Vadot these files. 22*5f62a964SEmmanuel Vadot There are several clocks that are generated outside the SoC. It is expected 23*5f62a964SEmmanuel Vadot that they are defined using standard clock bindings with following 24*5f62a964SEmmanuel Vadot clock-output-names: 25*5f62a964SEmmanuel Vadot - "xin24m" - crystal input - required, 26*5f62a964SEmmanuel Vadot - "clkin_i2s" - external I2S clock - optional, 27*5f62a964SEmmanuel Vadot - "gmac_clkin" - external GMAC clock - optional 28*5f62a964SEmmanuel Vadot - "phy_50m_out" - output clock of the pll in the mac phy 29*5f62a964SEmmanuel Vadot - "hdmi_phy" - output clock of the hdmi phy pll - optional 30*5f62a964SEmmanuel Vadot 31*5f62a964SEmmanuel Vadotproperties: 32*5f62a964SEmmanuel Vadot compatible: 33*5f62a964SEmmanuel Vadot enum: 34*5f62a964SEmmanuel Vadot - rockchip,rk3328-cru 35*5f62a964SEmmanuel Vadot 36*5f62a964SEmmanuel Vadot reg: 37*5f62a964SEmmanuel Vadot maxItems: 1 38*5f62a964SEmmanuel Vadot 39*5f62a964SEmmanuel Vadot "#clock-cells": 40*5f62a964SEmmanuel Vadot const: 1 41*5f62a964SEmmanuel Vadot 42*5f62a964SEmmanuel Vadot "#reset-cells": 43*5f62a964SEmmanuel Vadot const: 1 44*5f62a964SEmmanuel Vadot 45*5f62a964SEmmanuel Vadot clocks: 46*5f62a964SEmmanuel Vadot maxItems: 1 47*5f62a964SEmmanuel Vadot 48*5f62a964SEmmanuel Vadot clock-names: 49*5f62a964SEmmanuel Vadot const: xin24m 50*5f62a964SEmmanuel Vadot 51*5f62a964SEmmanuel Vadot rockchip,grf: 52*5f62a964SEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/phandle 53*5f62a964SEmmanuel Vadot description: 54*5f62a964SEmmanuel Vadot Phandle to the syscon managing the "general register files" (GRF), 55*5f62a964SEmmanuel Vadot if missing pll rates are not changeable, due to the missing pll 56*5f62a964SEmmanuel Vadot lock status. 57*5f62a964SEmmanuel Vadot 58*5f62a964SEmmanuel Vadotrequired: 59*5f62a964SEmmanuel Vadot - compatible 60*5f62a964SEmmanuel Vadot - reg 61*5f62a964SEmmanuel Vadot - "#clock-cells" 62*5f62a964SEmmanuel Vadot - "#reset-cells" 63*5f62a964SEmmanuel Vadot 64*5f62a964SEmmanuel VadotadditionalProperties: false 65*5f62a964SEmmanuel Vadot 66*5f62a964SEmmanuel Vadotexamples: 67*5f62a964SEmmanuel Vadot - | 68*5f62a964SEmmanuel Vadot cru: clock-controller@ff440000 { 69*5f62a964SEmmanuel Vadot compatible = "rockchip,rk3328-cru"; 70*5f62a964SEmmanuel Vadot reg = <0xff440000 0x1000>; 71*5f62a964SEmmanuel Vadot rockchip,grf = <&grf>; 72*5f62a964SEmmanuel Vadot #clock-cells = <1>; 73*5f62a964SEmmanuel Vadot #reset-cells = <1>; 74*5f62a964SEmmanuel Vadot }; 75