1* Rockchip RK3288 Clock and Reset Unit 2 3The RK3288 clock controller generates and supplies clock to various 4controllers within the SoC and also implements a reset controller for SoC 5peripherals. 6 7A revision of this SoC is available: rk3288w. The clock tree is a bit 8different so another dt-compatible is available. Noticed that it is only 9setting the difference but there is no automatic revision detection. This 10should be performed by bootloaders. 11 12Required Properties: 13 14- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in 15 case of this revision of Rockchip rk3288. 16- reg: physical base address of the controller and length of memory mapped 17 region. 18- #clock-cells: should be 1. 19- #reset-cells: should be 1. 20 21Optional Properties: 22 23- rockchip,grf: phandle to the syscon managing the "general register files" 24 If missing pll rates are not changeable, due to the missing pll lock status. 25 26Each clock is assigned an identifier and client nodes can use this identifier 27to specify the clock which they consume. All available clocks are defined as 28preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be 29used in device tree sources. Similar macros exist for the reset sources in 30these files. 31 32External clocks: 33 34There are several clocks that are generated outside the SoC. It is expected 35that they are defined using standard clock bindings with following 36clock-output-names: 37 - "xin24m" - crystal input - required, 38 - "xin32k" - rtc clock - optional, 39 - "ext_i2s" - external I2S clock - optional, 40 - "ext_hsadc" - external HSADC clock - optional, 41 - "ext_edp_24m" - external display port clock - optional, 42 - "ext_vip" - external VIP clock - optional, 43 - "ext_isp" - external ISP clock - optional, 44 - "ext_jtag" - external JTAG clock - optional 45 46Example: Clock controller node: 47 48 cru: cru@20000000 { 49 compatible = "rockchip,rk3188-cru"; 50 reg = <0x20000000 0x1000>; 51 rockchip,grf = <&grf>; 52 53 #clock-cells = <1>; 54 #reset-cells = <1>; 55 }; 56 57Example: UART controller node that consumes the clock generated by the clock 58 controller: 59 60 uart0: serial@10124000 { 61 compatible = "snps,dw-apb-uart"; 62 reg = <0x10124000 0x400>; 63 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 64 reg-shift = <2>; 65 reg-io-width = <1>; 66 clocks = <&cru SCLK_UART0>; 67 }; 68