1* Rockchip RK3188/RK3066 Clock and Reset Unit 2 3The RK3188/RK3066 clock controller generates and supplies clock to various 4controllers within the SoC and also implements a reset controller for SoC 5peripherals. 6 7Required Properties: 8 9- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or 10 "rockchip,rk3066a-cru" 11- reg: physical base address of the controller and length of memory mapped 12 region. 13- #clock-cells: should be 1. 14- #reset-cells: should be 1. 15 16Optional Properties: 17 18- rockchip,grf: phandle to the syscon managing the "general register files" 19 If missing pll rates are not changeable, due to the missing pll lock status. 20 21Each clock is assigned an identifier and client nodes can use this identifier 22to specify the clock which they consume. All available clocks are defined as 23preprocessor macros in the dt-bindings/clock/rk3188-cru.h and 24dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. 25Similar macros exist for the reset sources in these files. 26 27External clocks: 28 29There are several clocks that are generated outside the SoC. It is expected 30that they are defined using standard clock bindings with following 31clock-output-names: 32 - "xin24m" - crystal input - required, 33 - "xin32k" - rtc clock - optional, 34 - "xin27m" - 27mhz crystal input on rk3066 - optional, 35 - "ext_hsadc" - external HSADC clock - optional, 36 - "ext_cif0" - external camera clock - optional, 37 - "ext_rmii" - external RMII clock - optional, 38 - "ext_jtag" - externalJTAG clock - optional 39 40Example: Clock controller node: 41 42 cru: cru@20000000 { 43 compatible = "rockchip,rk3188-cru"; 44 reg = <0x20000000 0x1000>; 45 rockchip,grf = <&grf>; 46 47 #clock-cells = <1>; 48 #reset-cells = <1>; 49 }; 50 51Example: UART controller node that consumes the clock generated by the clock 52 controller: 53 54 uart0: serial@10124000 { 55 compatible = "snps,dw-apb-uart"; 56 reg = <0x10124000 0x400>; 57 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 58 reg-shift = <2>; 59 reg-io-width = <1>; 60 clocks = <&cru SCLK_UART0>; 61 }; 62