1* Rockchip PX30 Clock and Reset Unit 2 3The PX30 clock controller generates and supplies clock to various 4controllers within the SoC and also implements a reset controller for SoC 5peripherals. 6 7Required Properties: 8 9- compatible: PMU for CRU should be "rockchip,px30-pmu-cru" 10- compatible: CRU should be "rockchip,px30-cru" 11- reg: physical base address of the controller and length of memory mapped 12 region. 13- clocks: A list of phandle + clock-specifier pairs for the clocks listed 14 in clock-names 15- clock-names: Should contain the following: 16 - "xin24m" for both PMUCRU and CRU 17 - "gpll" for CRU (sourced from PMUCRU) 18- #clock-cells: should be 1. 19- #reset-cells: should be 1. 20 21Optional Properties: 22 23- rockchip,grf: phandle to the syscon managing the "general register files" 24 If missing, pll rates are not changeable, due to the missing pll lock status. 25 26Each clock is assigned an identifier and client nodes can use this identifier 27to specify the clock which they consume. All available clocks are defined as 28preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be 29used in device tree sources. Similar macros exist for the reset sources in 30these files. 31 32External clocks: 33 34There are several clocks that are generated outside the SoC. It is expected 35that they are defined using standard clock bindings with following 36clock-output-names: 37 - "xin24m" - crystal input - required, 38 - "xin32k" - rtc clock - optional, 39 - "i2sx_clkin" - external I2S clock - optional, 40 - "gmac_clkin" - external GMAC clock - optional 41 42Example: Clock controller node: 43 44 pmucru: clock-controller@ff2bc000 { 45 compatible = "rockchip,px30-pmucru"; 46 reg = <0x0 0xff2bc000 0x0 0x1000>; 47 #clock-cells = <1>; 48 #reset-cells = <1>; 49 }; 50 51 cru: clock-controller@ff2b0000 { 52 compatible = "rockchip,px30-cru"; 53 reg = <0x0 0xff2b0000 0x0 0x1000>; 54 rockchip,grf = <&grf>; 55 #clock-cells = <1>; 56 #reset-cells = <1>; 57 }; 58 59Example: UART controller node that consumes the clock generated by the clock 60 controller: 61 62 uart0: serial@ff030000 { 63 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 64 reg = <0x0 0xff030000 0x0 0x100>; 65 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 66 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 67 clock-names = "baudclk", "apb_pclk"; 68 reg-shift = <2>; 69 reg-io-width = <4>; 70 }; 71